coreboot April 2006

coreboot@coreboot.org

50 participants
115 discussions

Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

Committed. Also enable HT 1GHz support for s2891 and s2892. Thanks Yinghai Lu -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Lu, Yinghai Sent: Friday, March 31, 2006 5:24 PM To: Ronald G Minnich; Stefan Reinauer; Jason Schildt Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK Svn diff to current tree. Please check it. I will commit it some time next week. Guys have problem with s2891, s2881, s2892, please try it by patch -p0 to the latest tree. Changes 1. new CAR with copy data from cache to ram 2. new coherent_ht_car.c 3. new reset code for amd8111 4. new amd8111_early_ctrl without sysinfo... Thanks Yinghai Lu

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[LinuxBIOS] xp booting
by Stefan Reinauer 07 Apr '06

07 Apr '06

Hi, there's been quite some effort to get Windows XP running on Apple's new Intel Macs. And not all of it was by Apple. Interesting is that one guy opened his source code of an EFI compatibility handler. Maybe it is a good inspiration for LinuxBIOS? http://daemons.net/~clay/index.php/2006/03/15/dual-booting-windows-xp-and-m… http://daemons.net/~clay/OSXP/ Stefan

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Re: [LinuxBIOS] bus 0 dev 0 and fidvid change
by Lu, Yinghai 04 Apr '06

04 Apr '06

so what exactly does this do? It sets the position of an 8131 on a given bus? Does this work for all 8131 in a system? What about the 8111? And that 0 value - is that a special case? What is the connection to the other functionality? Does that mean there is only an 8111 and no 8131? Possible values: 0, 1, 6 ? Others? > HT_CHAIN_END_UNITID_BASE > Default is 0x20 --- mean do not use that, if it is 0, the > amd8111 will be dev0 do not use what? so i read: - HT_CHAIN_END_UNITID_BASE == 0x20: 8111 on bus 1 - HT_CHAIN_END_UNITID_BASE == 0x00: 8111 on bus 0 why end unitid base? how is the correlation to HT_CHAIN_UNITID_BASE? Possible values: 0, 32 ? Others? YH: A) 8131/8111 HT_CHAIN_UNITID_BASE=0x10, HT_CHAIN_END_UNITID_BASE=0x06 So 8131 will start from 0x10, and 8111 will start from 0x06 B) ck804 only HT_CHAIN_UNITD_BASE=0, So ck804 will start from 0x00. > SB_HT_CHAIN_UNITID_OFFSET_ONLY > Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset > unitid of SB CHAIN. Possible values: 0, 1? Others? What does that mean? Why would I only want to offset the unitid of the SB? SB Chain? Does it change the meaning of HT_CHAIN_UNITID_BASE? YH: 0: mean using HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE. > K8_SB_HT_CHAIN_ON_BUS0 > Deault is 0, if it is 1, will put sb chain on bus 0, even for > S2885 sb ht is on link2, it will put on bus0. does this require an 8111 southbrigde? YH: any SB chain > K8_SET_FIDVID in cache_as_ram_auto.c or auto.c > Fidvid change to sync the fid on 4 way or more system with different cpu > installed.... I thought SMP systems need identical CPUs installed, according to AMD BKDG? Is this option dangerous? Does it downclock faster CPUs to work sanely in SMP context? YH: A) using different CPU B) some MB can not use at MAX fid.... > Put following sequence in your cache_as_ram_auto.c after ht is set. > enable_fid_change(); > enable_fid_change_on_sb(); > init_fidvid_bsp(bsp_apicid); This is only needed if I want to use different CPUs? > please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for > detail.... Stefan

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[LinuxBIOS] bus 0 dev 0 and fidvid change
by Lu, Yinghai 04 Apr '06

04 Apr '06

Please check the issue 41, I make K8 MB can be compiled, and It include bus0/dev0 and fidvid change enhancement HT_CHAIN_UNITID_BASE Default is 1, and if it is 6, then amd8131 will be from 6, also if it is 0, will assume ht chain only have one HT device... HT_CHAIN_END_UNITID_BASE Default is 0x20 --- mean do not use that, if it is 0, the amd8111 will be dev0 SB_HT_CHAIN_UNITID_OFFSET_ONLY Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset unitid of SB CHAIN. K8_SB_HT_CHAIN_ON_BUS0 Deault is 0, if it is 1, will put sb chain on bus 0, even for S2885 sb ht is on link2, it will put on bus0. K8_SET_FIDVID in cache_as_ram_auto.c or auto.c Fidvid change to sync the fid on 4 way or more system with different cpu installed.... Put following sequence in your cache_as_ram_auto.c after ht is set. enable_fid_change(); enable_fid_change_on_sb(); init_fidvid_bsp(bsp_apicid); please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for detail.... YH

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[LinuxBIOS] Geode Utilities and Tools
by Bari Ari 04 Apr '06

04 Apr '06

Just FYI on the Geodes in case anyone missed them... The AMD Geode dev site has a few handy utilities and tools for debugging BIOS and driver settings. Cyreg - Cyreg is a menu driven utility that displays memory, I/O and PCI configuration space data. The menus are defined in a text file that allows the user to easily modify each menu. Loadreg - Loadreg is a command line utility that allows the user to read or modify any I/O, memory, or PCI configuration space location. It is ideally suited to modifying system registers via a batch file. MCVAL - Mcval tests the state of the memory controller against known values, as well as lists all supported processor speeds and their associated memory controller register values. -Bari

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Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards.
by Lu, Yinghai 04 Apr '06

04 Apr '06

Yes. -----Original Message----- From: Stefan Reinauer [mailto:stepan@coresystems.de] Sent: Monday, April 03, 2006 3:55 PM To: Lu, Yinghai Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards. * Lu, Yinghai <yinghai.lu(a)amd.com> [060403 23:25]: > Fixed. Please check again. It builds fine again. thanks. Should we drop reset.c from all amd64 mainboards? Stefan -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/

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[LinuxBIOS] Geode SC22000
by Per Hallsmark 04 Apr '06

04 Apr '06

Hello LB people, First, a great thank for the quick boost I had from your project in creating a special firmware for our project. I've ported LB to a SC2200 based platform, NCG266 (you can see some old photos at www.nano-system.com) The jump to the load just takes a couple of secs instead of like a minute with the Insyde BIOS... The LB base is svn ver 2171, I've got a 71K big patch for it. How do I contribute it to LB tree? Also during the learning and porting of LB, a couple of questions popped up: Q1: The source code files often include source files again instead of like building object modules that are later linked together. Why something like this? It seems odd to me as an perhaps oldschool C programmer. Q2: Why does the LB project need a special compiler? I've done numberous of firmware stuff and ordinary gnu tools have a good job so far. Must admit though that these hasn't been x86 which of course has it special boot mode, but there exist "standard" tools for that as well. (RPM package dev86 for example) Q3: Documentation... I was perhaps a bit optimistic when I thought the LB port should take one week, it was more like one month :-) But more documentation could help here a lot, or are there docs outside of linuxbios.org I've missed? Any work in progress here or can I contribute to it somehow? mvh Per Hallsmark T2 Data

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Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards.
by Lu, Yinghai 04 Apr '06

04 Apr '06

Fixed. Please check again. YH

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Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards.
by Stefan Reinauer 03 Apr '06

03 Apr '06

Yinghai, your latest checkin breaks _all_ opteron boards. in particular your "new reset functionality" - why exactly is that needed? Please go ahead and fix it. All opteron ports were compiling fine with r2231. compare http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2231.log and http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2232.log Stefan * svn(a)openbios.org <svn(a)openbios.org> [060403 22:38]: > Author: yhlu > Date: 2006-04-03 22:38:34 +0200 (Mon, 03 Apr 2006) > New Revision: 2232 > > Added: > trunk/LinuxBIOSv2/src/cpu/amd/car/clear_init_ram.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht_car.c > Modified: > trunk/LinuxBIOSv2/src/arch/i386/include/arch/romcc_io.h > trunk/LinuxBIOSv2/src/config/Options.lb > trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc > trunk/LinuxBIOSv2/src/cpu/amd/car/copy_and_run.c > trunk/LinuxBIOSv2/src/cpu/amd/car/disable_cache_as_ram.c > trunk/LinuxBIOSv2/src/cpu/amd/car/post_cache_as_ram.c > trunk/LinuxBIOSv2/src/cpu/amd/model_fxx/init_cpus.c > trunk/LinuxBIOSv2/src/cpu/x86/lapic/lapic_cpu_init.c > trunk/LinuxBIOSv2/src/devices/hypertransport.c > trunk/LinuxBIOSv2/src/include/cpu/x86/mem.h > trunk/LinuxBIOSv2/src/mainboard/agami/aruma/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/Config.lb > trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb > trunk/LinuxBIOSv2/src/mainboard/broadcom/blast/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2850/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2875/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2880/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2881/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2882/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2885/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/Options.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/get_bus_conf.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2891/resourcemap.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/Options.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2892/get_bus_conf.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/Options.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s2895/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s4880/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/Config.lb > trunk/LinuxBIOSv2/src/mainboard/tyan/s4882/cache_as_ram_auto.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/coherent_ht.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/incoherent_ht.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/raminit.c > trunk/LinuxBIOSv2/src/northbridge/amd/amdk8/reset_test.c > trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/Config.lb > trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_early_ctrl.c > trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_lpc.c > trunk/LinuxBIOSv2/src/southbridge/amd/amd8111/amd8111_reset.c > trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup.c > trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c > trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_enable_rom.c > trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_smbus.h > trunk/LinuxBIOSv2/targets/tyan/s2892/Config.lb > trunk/LinuxBIOSv2/targets/tyan/s2895/Config.lb > Log: > new cache_as_ram support -- coresystems GmbH · Brahmsstr. 16 · D-79104 Freiburg i. Br. Tel.: +49 761 7668825 · Fax: +49 761 7664613 Email: info(a)coresystems.de · http://www.coresystems.de/

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[LinuxBIOS] linuxbios on nodes?
by ulrich.vanbrakel＠pr0sys.com 03 Apr '06

03 Apr '06

Hi everyone, regarding linuxbios: Do I have to load linuxbios on both "server PC" and nodes, or can I get away with loading it on the nodes only? ps. if this is any help, I am planning on using Clustermatic ..

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coreboot April 2006