so what exactly does this do? It sets the position of an 8131 on a given bus? Does this work for all 8131 in a system? What about the 8111?
And that 0 value - is that a special case? What is the connection to the other functionality? Does that mean there is only an 8111 and no 8131?
Possible values: 0, 1, 6 ? Others?
HT_CHAIN_END_UNITID_BASE Default is 0x20 --- mean do not use that, if it is 0, the amd8111 will be dev0
do not use what? so i read: - HT_CHAIN_END_UNITID_BASE == 0x20: 8111 on bus 1 - HT_CHAIN_END_UNITID_BASE == 0x00: 8111 on bus 0
why end unitid base? how is the correlation to HT_CHAIN_UNITID_BASE?
Possible values: 0, 32 ? Others?
YH: A) 8131/8111 HT_CHAIN_UNITID_BASE=0x10, HT_CHAIN_END_UNITID_BASE=0x06 So 8131 will start from 0x10, and 8111 will start from 0x06 B) ck804 only HT_CHAIN_UNITD_BASE=0, So ck804 will start from 0x00.
SB_HT_CHAIN_UNITID_OFFSET_ONLY Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset unitid of SB CHAIN.
Possible values: 0, 1? Others?
What does that mean? Why would I only want to offset the unitid of the SB? SB Chain? Does it change the meaning of HT_CHAIN_UNITID_BASE?
YH: 0: mean using HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE.
K8_SB_HT_CHAIN_ON_BUS0 Deault is 0, if it is 1, will put sb chain on bus 0, even for S2885 sb ht is on link2, it will put on bus0.
does this require an 8111 southbrigde?
YH: any SB chain
K8_SET_FIDVID in cache_as_ram_auto.c or auto.c
Fidvid change to sync the fid on 4 way or more system with different
I thought SMP systems need identical CPUs installed, according to AMD BKDG? Is this option dangerous? Does it downclock faster CPUs to work sanely in SMP context?
YH: A) using different CPU B) some MB can not use at MAX fid....
Put following sequence in your cache_as_ram_auto.c after ht is set. enable_fid_change(); enable_fid_change_on_sb(); init_fidvid_bsp(bsp_apicid);
This is only needed if I want to use different CPUs?
please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for detail....