coreboot January 2004

coreboot@coreboot.org

44 participants
99 discussions

答复: Two console in com1 and com2 in
by YhLu 16 Jan '04

16 Jan '04

Thanks, Current our Server Management Daughter card (SMDC or IPMI card) is using COM2 on MB to do Console redirection via LAN. So If using LinuxBIOS, I also hope the user use COM1 for on site Console using if he he wants. Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年1月15日 22:11 收件人: YhLu 抄送: ron minnich; linuxbios(a)clustermatic.org 主题: Re: Two console in com1 and com2 in YhLu <YhLu(a)tyan.com> writes: > Eric, > > I wonder if it is possible to have two consoles and one is in com1 and the > other is in com2, and maybe in different baud rate. > > I mean in LinuxBIOS should be OK if I add another uart8250_console2.c. but > how about Etherboot, Does it support that? Or just can only use one port? Etherboot would need similar modifications but it can support two consoles as well. What would be the gain in having two serial consoles? Eric

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Two console in com1 and com2 in
by YhLu 15 Jan '04

15 Jan '04

Eric, I wonder if it is possible to have two consoles and one is in com1 and the other is in com2, and maybe in different baud rate. I mean in LinuxBIOS should be OK if I add another uart8250_console2.c. but how about Etherboot, Does it support that? Or just can only use one port? Regards Yinghai Lu

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LC2430 - laptop candidate for LinuxBIOS (Intel 845G)?
by Miernik 15 Jan '04

15 Jan '04

Maybe this will be a candidate for LinuxBIOS laptop: http://www.linuxcertified.com/linux-laptop-lc2430.html This laptop is probably produced by a Linux company (LC stands for Linux Certified I presume), so they might be interested in cooperation. It has been recently Debian certified. The chipsets are: http://www.linuxcertified.com/specs_lc2430.html Host bridge: Intel Corp. 82845G/GL [Brookdale-G] Chipset Host Bridge There are some datasheets for this here: http://developer.intel.com/design/chipsets/845/ lspci optput is here: http://www.linuxcertified.com/test-reports/lc2430-report/debian-info.epl.ht… There has been one post on the LinuxBIOS list, from someone who says that he has done some Intel 845 work: http://www.clustermatic.org/pipermail/linuxbios/2002-September/000239.html -- JabberID:miernik@amessage.info

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legacy vga ... what do you think?
by ron minnich 15 Jan '04

15 Jan '04

The issue is that at the amdk8 northbridge, we need to know bus/dev/fn for the hardware so we can set up the VGA_EN bit in the right PCIIO pair as well as an MMIO entry for it. It's not enough to just set a bit in the bridge on the K8 -- you have to set up routing to the right Hypertransport bus. You have to know where the device is. By far the easiest way to do this is to add a simple structure member to the bus structure: struct device *vgadev; so we have: struct bus { device_t dev; /* This bridge device */ device_t children; /* devices behind this bridge */ unsigned bridge_ctrl; /* Bridge control register */ /* NEW */ struct device *vgadev; /* if bridge_ctl has * PCI_CB_BRIDGE_CTL_VGA set, * this contains pointer to * the device. */ /* END NEW */ unsigned char link; /* The index of this link */ unsigned char secondary; /* secondary bus number */ unsigned char subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ }; Setting vgadev is then trivial in the allocate_vga_resource since in that function you already have a pointer to the vga device; or just set the pointer. Either way, when you are at a bridge and know that the bridge has vga on the bus somewhere, you can easily get the info you need to set up the bridge if it is a complex bridge like the K8. while(bus) { bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; /* NEW */ bus->vgadev = vga; /* END NEW */ bus = (bus == bus->dev->bus)? 0 : bus->dev->bus; } Unless there is a huge problem with this I will try to get it done tomorrow. It's a new structure member and one line of code and we're on the air. It is not totally general but ... VGA is "special". As in, really ugly. ron

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VGA console on S2885 with fbdev
by Hendricks David W. 15 Jan '04

15 Jan '04

If you need a VGA console for an S2885, fbdev seems to work pretty well, at least with the GeForce 2 MX we've tested it with. Just rip your video BIOS (dd if=/dev/mem of=vgabios.bin count=1536 skip=128), run testbios -s 65336 vgabios.bin, and modprobe your fbdev driver. Only obvious issue we noticed was when quitting X the cursor became grossly out of proportion. It's really kind of funny (Assuming you have no real work to get done). Kind of a quick workaround, but if you're desperate for a local console fbdev seems to be a good temporary solution.

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New LinuxBIOS user needs urgent help!
by Maciej Olesiński 15 Jan '04

15 Jan '04

Hello! When I first encountered LinuxBIOS project at the beginning of december, I was amazed at what it can do (for example I would like to build my OWN mini router DoC distro). So the next day I found M-Sys distributor in Poland and ordered two MD2802-D08 units, because I had two spare mobo's with BX chipset. After 4 (!!!) weeks of waiting I finally got my DoCs and began my story with LinuxBIOS begun. First thaing that was wrong, was that docipl file was missing, but I tried not to bother about that. It took me a few days before I read on the linuxbios newsgroup that BX is not supported in the way I would like it to be. I also learned that SiS got very good support (now I know it HAD, but hasn't any more), so I tried to buy used SiS 630/635/730/735 chipset based mainboard, because I saw they all got ipl.S file in their folders. After one week I finally found nice board based on SiS 735 (Ellitegroup's K7S5A) and I bought it. I patched kernel for use with SiS and tried to build rom images for my new SiS. Then something terrible happened! I got error during compilation of docipl file, saying that .org instruction is moving backwards! Once again I looked up newsgroup and read that SiS 735 with DoC is _NOT_ supported. That's why I got a few questions: 1. Which *NEW* mainboard can I buy if I want to install LinuxBIOS with DoC Millenium support on it? 2. How mature is freebios2 project? 3. Does IPL code for SiS 735 initialize only DDR SDRAM (no standard SDRAM) or both? (I got normal SDRAM in my mobo) 4. If I get it right SiS 735 cannot boot off MD2802-D08 because it's IPL code is too big? 5. Any idea why my flash writer does not work on mobo ECS K7S5A, based on SiS 735 with IT8705F superio (which is 100% compatible with SiS 950)? I use "flash_on" utility for SiS and if I'm right it should work on this nb/sb/sio configuration, but "flash_rom" says "no EEPROM". Thanks for any help, Uszaty

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Re: Support for Athlon 64 and nVIDIA nforce3
by Stefan Reinauer 14 Jan '04

14 Jan '04

* Mayuresh Bakshi <mayuresh.bakshi(a)nevisnetworks.com> [040115 09:15]: > > Hi, > > We've a custom board with AMD Athlon 64 processor > and nVIDIA nforce3 as south bridge. Does linuxBIOS > have support for these chipsets. nvidia nforce3 is not supported. AFAIK nvidia has been kind of restrictive wrt releasing any of their specs. Only AMD released the complete range to their specifications and data sheets for AMD64 chipsets. Best regards, Stefan Reinauer -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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Support for Athlon 64 and nVIDIA nforce3
by Mayuresh Bakshi 14 Jan '04

14 Jan '04

Hi, We've a custom board with AMD Athlon 64 processor and nVIDIA nforce3 as south bridge. Does linuxBIOS have support for these chipsets. Thanks, -Mayuresh

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SuperIO w83627hf. support.
by YhLu 14 Jan '04

14 Jan '04

Eric or Ron or Stefan,, I want to who's dev src/superio/NSC/pc87360. I have tried to copy and modify for winbond/w83627hf to make FDC and Keyboard to work. Some resource can not be set to the several reg. I add several line in s2282/Config.lb superio winbond/w83627hf link 1 pnp 2e.0 pnp 2e.1 pnp 2e.2 pnp 2e.3 pnp 2e.5 pnp 2e.6 pnp 2e.7 pnp 2e.8 pnp 2e.9 pnp 2e.a pnp 2e.b register "com1" = "{1, 0, 0x3f8, 4}" register "lpt" = "{1}" end Can you tell why call it 2e... Regards YH. the result will be Allocating resources... PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.5 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.5 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 01:04.5 missing read_resources PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00003fff] node 0 link 0 io PCI: 01:04.5 missing read_resources PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xfd000000 - 0xfe2fffff] node 0 link 0 mem ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00001000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xfe200000 - 0xfe1fffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xfe100000 - 0xfe1fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:06.0 10 <- [0x00001000 - 0x000010ff] io PCI: 02:06.0 14 <- [0xfe140000 - 0xfe141fff] mem PCI: 02:06.0 1c <- [0x00001400 - 0x000014ff] io PCI: 02:06.1 10 <- [0x00001800 - 0x000018ff] io PCI: 02:06.1 14 <- [0xfe142000 - 0xfe143fff] mem PCI: 02:06.1 1c <- [0x00001c00 - 0x00001cff] io PCI: 02:09.0 10 <- [0xfe100000 - 0xfe10ffff] mem PCI: 02:09.0 18 <- [0xfe110000 - 0xfe11ffff] mem PCI: 02:09.1 10 <- [0xfe120000 - 0xfe12ffff] mem PCI: 02:09.1 18 <- [0xfe130000 - 0xfe13ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xfe200000 - 0xfe200fff] mem PCI: 01:02.0 1c <- [0x00003000 - 0x00002fff] bus 3 io PCI: 01:02.0 24 <- [0xfe200000 - 0xfe1fffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xfe200000 - 0xfe1fffff] bus 3 mem PCI: 01:02.1 10 <- [0xfe201000 - 0xfe201fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00002000 - 0x00002fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xfe200000 - 0xfe1fffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xfd000000 - 0xfeffffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xfe020000 - 0xfe020fff] mem PCI: 04:00.1 10 <- [0xfe021000 - 0xfe021fff] mem PCI: 04:00.2 10 <- [0xfe025000 - 0xfe0250ff] mem PCI: 04:00.2 14 <- [0xfe026000 - 0xfe02601f] mem PCI: 04:01.0 missing set_resources PCI: 04:05.0 10 <- [0x00002450 - 0x00002457] io PCI: 04:05.0 14 <- [0x00002470 - 0x00002473] io PCI: 04:05.0 18 <- [0x00002460 - 0x00002467] io PCI: 04:05.0 1c <- [0x00002480 - 0x00002483] io PCI: 04:05.0 20 <- [0x00002440 - 0x0000244f] io PCI: 04:05.0 24 <- [0xfe024000 - 0xfe0243ff] mem PCI: 04:06.0 10 <- [0xfd000000 - 0xfdffffff] mem PCI: 04:06.0 14 <- [0x00002000 - 0x000020ff] io PCI: 04:06.0 18 <- [0xfe022000 - 0xfe022fff] mem PCI: 04:08.0 10 <- [0xfe023000 - 0xfe023fff] mem PCI: 04:08.0 14 <- [0x00002400 - 0x0000243f] io PCI: 04:08.0 18 <- [0xfe000000 - 0xfe01ffff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem ASSIGN RESOURCES, bus 0 PNP: 002e.0 60 <- [0x00003030 - 0x00003037 io ERROR: PNP: 002e.0 70 not allocated ERROR: PNP: 002e.0 74 not allocated PNP: 002e.1 60 <- [0x00003040 - 0x00003047 io ERROR: PNP: 002e.1 70 not allocated ERROR: PNP: 002e.1 74 not allocated PNP: 002e.2 60 <- [0x000003f8 - 0x000003f7 io PNP: 002e.2 70 <- [0x00000004 - 0x00000003 irq PNP: 002e.3 60 <- [0x00003050 - 0x00003057 io ERROR: PNP: 002e.3 70 not allocated PNP: 002e.5 60 <- [0x00000060 - 0x0000005f io PNP: 002e.5 62 <- [0x00000064 - 0x00000063 io PNP: 002e.5 70 <- [0x00000001 - 0x00000000 irq PNP: 002e.5 72 <- [0x0000000c - 0x0000000b irq PNP: 002e.6 60 <- [0x00003060 - 0x00003067 io ERROR: PNP: 002e.6 70 not allocated PNP: 002e.7 60 <- [0x00003090 - 0x00003090 io PNP: 002e.7 62 <- [0x00003080 - 0x00003081 io ERROR: PNP: 002e.7 70 not allocated ERROR: PNP: 002e.a 70 not allocated PNP: 002e.b 60 <- [0x00003070 - 0x00003077 io ERROR: PNP: 002e.b 70 not allocated ASSIGNED RESOURCES, bus 0 PCI: 01:04.1 20 <- [0x00003020 - 0x0000302f] io PCI: 01:04.2 10 <- [0x00003000 - 0x0000301f] io PCI: 01:04.5 missing set_resources PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource

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答复: SuperIO w83627hf. support.
by YhLu 14 Jan '04

14 Jan '04

Yes, may only sio_enable() and struct pnp_dev_info[] and enumerate should be specific. YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年1月14日 16:50 收件人: YhLu 抄送: ron minnich; linuxbios(a)clustermatic.org 主题: Re: SuperIO w83627hf. support. YhLu <YhLu(a)tyan.com> writes: > Eric or Ron or Stefan,, > > I want to who's dev src/superio/NSC/pc87360. > > I have tried to copy and modify for winbond/w83627hf to make FDC and > Keyboard to work. Some resource can not be set to the several reg. The only piece I am seeing, is that the irq resources that are not hard coded are not being allocated automatically. The basic problem is that we don't have an irq allocator in LinuxBIOS, We also could use a legacy address allocator as well to automatically put these things at their legacy addresses if possible. My latest build (still needs to be merged) I just turned off all of the devices I didn't care about which made the irq assignment problems go away. It is a bad long term solution but it is ok in the short term. > Can you tell why call it 2e... Because that is the base configuration port. Figuring out what kind of paths to use for devices like this is a bit of a challenge. I forget but I think there was a considerable about of infrastructure in the super.c file you copied that probably should be moved to a generic file some place. Eric

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coreboot January 2004