coreboot January 2004

coreboot@coreboot.org

44 participants
99 discussions

Re: EPIA-M HW graphics slow under linuxbios
by Dave Ashley 29 Jan '04

29 Jan '04

That old patch: http://www.clustermatic.org/pipermail/linuxbios/2003-July/004046.html was the first one I put up, there have been a lot of fixes since then. Go to this site: http://www.xdr.com/dash/linuxbios/ get this patch: http://www.xdr.com/dash/linuxbios/freebios-nxtv-patch-20030705.gz That is more complete. The slow video rendering might be related to the int21 handlers in mainboard.c. I found performance wasn't as good as under award bios until I fixed that. It looks like the patch you applied doesn't even handle the bios callbacks the VGA bios is expecting. -Dave

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Re: EPIA-M HW graphics slow under linuxbios
by Dave Ashley 29 Jan '04

29 Jan '04

>I did what you said... >... >Jumping to boot code at 0x106710 >0 I think this is a divide by zero error when it tries to jump into the etherboot payload. Etherboot has a bug which I've mentioned before. It tries to use some timer machinery before it has been initialized. Edit src/timer.c of etherboot, in the function currticks you want: diff -Nur etherboot-5.0.10/src/timer.c etherboot-5.0.10-new/src/timer.c --- etherboot-5.0.10/src/timer.c Sat Mar 22 11:52:25 2003 +++ etherboot-5.0.10-new/src/timer.c Wed Jul 16 09:45:46 2003 @@ -138,6 +138,8 @@ { unsigned long clocks_high, clocks_low; unsigned long currticks; + +setup_timers(); /* Read the Time Stamp Counter */ rdtsc(clocks_low, clocks_high); BTW if this fixed your problem I'm a miracle worker. -Dave

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FYI: An interesting note about intels x86-64 plans
by ebiederman＠lnxi.com 29 Jan '04

29 Jan '04

http://www.reuters.com/newsArticle.jhtml?type=technologyNews&storyID=4233918 Eric

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old config method
by Stefan Reinauer 28 Jan '04

28 Jan '04

Hi, I've dropped the configuration files of the old configuration method today to keep the LinuxBIOS 2 codebase as clean as possible. Since all ports use the new configuration method now, these files were obsolete and only there for reference. Best regards, Stefan Reinauer -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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question re: epox 8rda+
by Matthew Lucas 28 Jan '04

28 Jan '04

Dear LinuxBios group, I've been lurking on the list for about two weeks. After checking the product listings on the website, I have not found a listing for the mother board I use. Has anyone successfully installed a linux bios on an Epox 8rda+ Ultra 400 nforce2? It uses the Phoenix Awardbios v6.0. Thanks for any info, Matthew Lucas Chicago, IL

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Updated PPC support
by Greg Watson 28 Jan '04

28 Jan '04

For those interested in PPC issues, I have updated support for the Motorola Sandpoint (G4 processor) in the V2 tree. Over the next few days I will tidy up a few remaining things, but as of now I have the Sandpoint booting a 2.4.24-pre2 kernel. Regards, Greg

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ACPI Support
by Stefan Reinauer 28 Jan '04

28 Jan '04

Hi, I've implemented initial code for ACPI support in LinuxBIOS. It can be enabled by the option HAVE_ACPI_TABLES. Currently there is only support for HPET tables, which are needed to tell the Linux kernel where the HPET timers on AMD64 systems can be found. The code is generated at the same place as the other tables (MP/PIRQ) - in src/arch/i386/boot/tables.c. The ACPI code itself can be found at src/arch/i386/boot/acpi.c The code is far from being a generic ACPI implementation, but it can be enhanced to whatever is needed. Questions and comments are welcome. Best regards, Stefan Reinauer -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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LPC Rom Programmer/Emulator Recommendations
by Don Elwell 28 Jan '04

28 Jan '04

All, I just discovered that my good old BP-1200 Universal Device Programmer isn't quite so universal -- it won't program LPC based firmware BIOS flash devices. Anyone got any sort of recommendations on an LPC flash compatible programmer? One that runs under Linux perhaps? Better yet, what about an LPC flash ROM emulator? -don

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Couple of questions...
by John Szakmeister 27 Jan '04

27 Jan '04

Is there directions on how to build LinuxBIOS somewhere? I haven't seen much in the way of documentation, but I'd like to give it a whirl. Also, I'm not sure my motherboard is supported. I have an ASUS A7M266-D (it's a dual proc AMD motherboard). Here is the 'lspci' output: 00:00.0 Host bridge: Advanced Micro Devices [AMD] AMD-760 MP [IGD4-2P] System Controller (rev 11) 00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-760 MP [IGD4-2P] AGP Bridge 00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-768 [Opus] ISA (rev 04) 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-768 [Opus] IDE (rev 04) 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-768 [Opus] ACPI (rev 03) 00:09.0 FireWire (IEEE 1394): Texas Instruments TSB12LV26 IEEE-1394 Controller (Link) 00:10.0 PCI bridge: Advanced Micro Devices [AMD] AMD-768 [Opus] PCI (rev 04) 01:05.0 VGA compatible controller: nVidia Corporation NV11 [GeForce2 MX/MX 400] (rev a1) 02:04.0 Multimedia audio controller: C-Media Electronics Inc CM8738 (rev 10) 02:05.0 Ethernet controller: Digital Equipment Corporation DECchip 21140 [FasterNet] (rev 22) 02:06.0 USB Controller: NEC Corporation USB (rev 41) 02:06.1 USB Controller: NEC Corporation USB (rev 41) 02:06.2 USB Controller: NEC Corporation USB 2.0 (rev 02) BTW, read the recent article in Linux Journal... this is really cool stuff. -John

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Re: Link/Links field in struct device
by ebiederman＠lnxi.com 27 Jan '04

27 Jan '04

Li-Ta Lo <ollie(a)lanl.gov> writes: > Eric, > > What does the link field in the device struct used for ? Does > it has anything to do with the hypertransport links ? Yes, and no. In the device tree each device has several links coming off of it. One for each function. So below mc0 has 6 logical links: pci 0:18.0 pci 0:18.0 pci 0:18.0 pci 0:18.1 pci 0:18.2 pci 0:18.3 You can only hang devices off of the first 3 which are the hypertransport links, in this case. Hanging devices off the rest is not physically possible. I do abuse HT chains a little bit an consider all of their members hanging off the start of the chain instead of hanging off of each other. But that seems to model the reality fairly well. > Is there a way to travel the HT links like the PCI bus in LinuxBIOS ? Yes. A HT chain is treated as a bus. And we rebuild the chains during enumeration. > > Ollie northbridge amd/amdk8 "mc0" pci 0:18.0 pci 0:18.0 pci 0:18.0 pci 0:18.1 pci 0:18.2 pci 0:18.3 southbridge amd/amd8131 "amd8131" link 0 end southbridge amd/amd8111 "amd8111" link 0 end end

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coreboot January 2004