Can anyone who has built a k7sem recently verify that the 'FIXED MTRR set
to UC' code is not fouling up the K7sem?
I really do want to freeze the 1.0 tree but we're not converging. Or we
almost are save for "the last few bugs". I just got some K7SEM's but won't
have time to look at this for a bit -- if anyone can test this for me with
the latest CVS that would be helpful.
Andrew Ip, you are probably the best person to test this, can you take a
I just stumbled over your new webpage http://www.linuxbios.org/
I've read some of the stuff there, and I simply loved that idea.
I subscribed to get a grasp of what currently is going on at the
linuxBIOS development. My motherboard is Abit VP6 dual PIII, maybe at
some point in the future it will get support. And I'll be the first
tester ;) Anyway I must get a grasp of all this stuff to understand
what's going on :)
First of all - May I make some notices to the LinuxBIOS team? ;)
1. I've read FAQ. But althought I've read the whole FAQ I didn't get the
answer for one question.
- what is DoS ?
(there are answers about how to prepare DoS, but not what is DoS by itself)
- on second thought - wouldn't it be nice if you place some email addres
on the webpage. for example in the FAQ section. "do you have a question
not answered in the FAQ? email this question to us". If you don't want
spambots to collect this email address - display it as an image with
text written on it. Spambots cannot (yet) collect email addresses from
2. If you are interested I can offer you some little help with LinuxBIOS
webpage. I'm currently working on some php scripts designed to make easy
management of webpage contents (I called it GNU/enjine ;).
The easy management is achieved by creating a menu file, which contains
information about what is to be displayed. Now you don't have to edit
the html, but just the menu.
Short descripton with testing of some features is here:
An example usage of enjine (my computer usage/load graphs made with
# Janek Kozicki
On Mon, 23 Jun 2003, rickytato wrote:
> Hi Ron, I'm rickytato, I want to know if the pc-chips M830LR are
> supported by linuxbios. on the web site the status are unstable, but I
> think that web site aren't upgrade.
I am not sure any more. We'll have to ask the list. Who owns that board?
I read an articel about the Linux BIOS Project in the Linux-Magazin
What i want to know is: "Does anybody think about using in
Dynatools Communication Services GmbH
i have an old gigabyte board with the 430TX chipset on it. For
configuration i used the example from
src/mainborads/digitallogic/smartcore-p5/config.example, because it uses
the 430tx as northbridge and the piix4 as southbridge as my board does.
After running the python program, i started to make a romimage. But i
don't get the docipl file after make finshed. What can i do?
This is my lspci output:
00:00.0 Host bridge: Intel Corp. 430TX - 82439TX MTXC (rev 01)
00:07.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 01)
00:07.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01)
00:07.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01)
00:07.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 01)
00:08.0 VGA compatible controller: Matrox Graphics, Inc. MGA 2164W
00:0a.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone]
Oops... Sent this dirctly to ron instead of the list like I wanted.
ron minnich wrote:
> I'm not checked out on this particular problem, most of my nodes don't do
> mice. :-(
I solved my no mouse issues. The problem was that the keyboard_on() in
southbridge.c was setting the KBCSS# enable bit and I didn't realize it.
The KBCSS# enable causes the piix4e to assert KBCS# and XOE# upon access
to io ports 60 and 64. These are basically chip selects for a setup
that dosn't have decoding of these io port build in. Our NSC PC87351
superio dosen't need these lines as it does its own IO decodeing of
these ports. And even though these lines aren't hooked to anything on
our board if this bit is enabled then the mouse won't work. Kinda of
wierd since the keyboard works fine and they both use the same IO addresses.
So this enable needs to be an option rather than hardcoded as its
motherboard dependant if you need this bit set or not. I suspect that
almost all modern superios will _not_ need any help with IO decode so
I'll default this to off.
Ron: did you ever attempt to sync the 440bx code with patch file I sent
you? If not then don't worry about it as I have change quite a bit
since then. Most of it is just a lot of addtional prink_debugs to show
what the code is doing and where it happens but there is a fix or 2 in
there as well. I'm also adding some things like getting the USB bridge
setup right. Linux still whines about not being able to get the irq.
Richard A. Smith