coreboot June 2003

coreboot@coreboot.org

55 participants
94 discussions

freebios2 + k8 users
by ron minnich 25 Jun '03

25 Jun '03

Just to make sure I'm in sync, I'm assuming you all are building fallback images only? Or are you building normal images? I'm building fallback but ... ron

2 1

re: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
by YhLu 25 Jun '03

25 Jun '03

Ron, I use 16M ramdisk that will downloaded into Node with Kernel at the same time. So didn't use MTD etc. Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年6月25日 9:08 收件人: Eric W. Biederman 抄送: linuxbios(a)clustermatic.org 主题: Re: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD On 25 Jun 2003, Eric W. Biederman wrote: > That is what I have working right now. just checking, you're running the 64-bit kernel? I guess I'll yank down the newest MTD cvs and try again. ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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re: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
by YhLu 25 Jun '03

25 Jun '03

Ron, Did you use SMP support or not? I use NON-SMP support in Tyan S2880 and it die in the Kernel too. Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年6月25日 8:13 收件人: linuxbios(a)clustermatic.org 主题: K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD The above combination works pretty well until I try to program the part, at which point the kernel takes an oops and dies. I'm wondering if anyone else has either: - seen this work - seen this fail thanks ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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K8 + 2.4.21 + SuSE 64-bit mode + Arima HDAMA + 49LF040 + MTD
by ron minnich 25 Jun '03

25 Jun '03

The above combination works pretty well until I try to program the part, at which point the kernel takes an oops and dies. I'm wondering if anyone else has either: - seen this work - seen this fail thanks ron

2 2

freebios2: pcibios_read_config_*
by ron minnich 25 Jun '03

25 Jun '03

these appear to be deprecated? Just checking as they are not in my freebios2 tree any more but code that uses them is still there. ron

2 2

romcc ramblings...
by ebiederman＠lnxi.com 25 Jun '03

25 Jun '03

Romcc is coming along quite nicely. I keep fixing a corner case here and there but it quite usable and getting more so. One area where it falls short is in it's handling of lots of small variables. The classic question is: If I declare my small variables to be chars will romcc be able to store them in both AL and AH? And unfortunately the answer is no. Using the AH, BH, CH, and DH at least when I tried it did not work well. Treating all of the registers the same seems to work much better. A similar question is can romcc pack 2 byte values in a random register? The answer again is no. But for a different reason extracting and reinserting the values requires an extra register, so it is not a transformation I want to perform automatically. With that being said I do think it is worth having romcc support keeping multiple values in a register. Otherwise I will wind up writing a bunch of macros like: #define LATENCY(MIN) (((MIN) >> 8) & 0xff) #define SET_LATENCY(MIN, LATENCY) ((MIN) = (((MIN) & ~(0xff << 8)) | (((LATENCY) & 0xFF) << 8))) #define CYCLE_TIME(MIN) ((MIN) & 0xff) #define SET_CYCLE_TIME(MIN, CYCLE_TIME) ((MIN) = (((MIN) & ~0xff) | ((CYCLE_TIME) & 0xFF))) Which look ugly are a bit of a pain to write. I looked an C actually has a mechanism to do this already. bit fields in structures. For doing I/O to the outside world they are not portable. So their use is discouraged. For internal values that are just going to be used internally by a program, say packing multiple values in a single register they are portable and a decent way to describe what is going on. So to keep 2 byte values in I register I could do: struct { unsigned latency:8; unsigned cycle_time:8; } min; I have not implemented this but I plan to. For both programmer control and ease of use it looks like a win. Eric

1 0

romcc ramblings...
by ebiederman＠lnxi.com 25 Jun '03

25 Jun '03

Romcc is coming along quite nicely. I keep fixing a corner case here and there but it quite usable and getting more so. One area where it falls short is in it's handling of lots of small variables. The classic question is: If I declare my small variables to be chars will romcc be able to store them in both AL and AH? And unfortunately the answer is no. Using the AH, BH, CH, and DH at least when I tried it did not work well. Treating all of the registers the same seems to work much better. A similar question is can romcc pack 2 byte values in a random register? The answer again is no. But for a different reason extracting and reinserting the values requires an extra register, so it is not a transformation I want to perform automatically. With that being said I do think it is worth having romcc support keeping multiple values in a register. Otherwise I will wind up writing a bunch of macros like: #define LATENCY(MIN) (((MIN) >> 8) & 0xff) #define SET_LATENCY(MIN, LATENCY) ((MIN) = (((MIN) & ~(0xff << 8)) | (((LATENCY) & 0xFF) << 8))) #define CYCLE_TIME(MIN) ((MIN) & 0xff) #define SET_CYCLE_TIME(MIN, CYCLE_TIME) ((MIN) = (((MIN) & ~0xff) | #((CYCLE_TIME) & 0xFF))) So many times while in your registers you have enough bits to hold everything you want to hold Theoretically

1 0

re: coherent hypertransport enumeration on opteron
by YhLu 25 Jun '03

25 Jun '03

Eric, The RAM on CPU1's northbridge can go through now. I mistype several 0x19 to 0x18. I have enabled the SMP support in Config file. option CONFIG_SMP=1 option MAX_CPUS=2 option SMP=1 As for the missing functions. I have copied secondCPU.S and udelay related files to the freebios2. The result is it can not jumping into LinuxBIOS again. In the Config last line you said something need to be fixed up. Do I need to change the START_CPU_SEG ? Regards Yinghai Lu

3 2

Re: coherent hypertransport enumeration on opteron
by YhLu 25 Jun '03

25 Jun '03

Eric, Do you plan use CONFIG_SMP to substitute SMP? Regards Yinghai Lu -----邮件原件----- 发件人: YhLu 发送时间: 2003年6月24日 16:37 收件人: 'ebiederman(a)lnxi.com' 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: re: coherent hypertransport enumeration on opteron Eric, The RAM on CPU1's northbridge can go through now. I mistype several 0x19 to 0x18. I have enabled the SMP support in Config file. option CONFIG_SMP=1 option MAX_CPUS=2 option SMP=1 As for the missing functions. I have copied secondCPU.S and udelay related files to the freebios2. The result is it can not jumping into LinuxBIOS again. In the Config last line you said something need to be fixed up. Do I need to change the START_CPU_SEG ? Regards Yinghai Lu

2 1

Re: Laptops?
by Bari Ari 25 Jun '03

25 Jun '03

Jeff Carr wrote: >I don't know any more than the output of lspci. I've not tried to open >up the case to see the full board. I've still not been able to get power >management to work after re-installing it with debian. (sound, USB 2.0 >and ethernet work ok.) > >Jeff > >FYI: The portable came without any sources. I sent a inquiry about how >to get them on the website of the people that sold the machine to me, >but no one responded. (A HUGE GPL violation.) When I re-installed with >debian, I found the power management(and several other drivers) were >only in the lindows kernel and I not been able to get them to work >since. It doens't look like they drivers from the lindows kernel are in >any of the kernel sources I can find. So, in that regard, angry about >how "linux support" was provided for this portable would be too light of >a description. > > Not surprising on the loss of power management when you dropped Lindows. They are probably using a laptop super I/O with a keyboard controller (8051 micro with lots of GPIO) by SMSC or a micro by Renasas or Fujitsu to handle the keyboard scan and power management. Some descriptions of the firmware and what they use these micros for: http://www.insydesw.com/solutions/pc/keyboard.htm http://www.phoenix.com/en/products/phoenix+cme+firstbios/system+firmware/te… -Bari

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coreboot June 2003