coreboot April 2003

coreboot@coreboot.org

68 participants
177 discussions

intel firmware hub parts
by ron minnich 13 May '03

13 May '03

has anyone found a distributor for these parts? this is really amazing, but nobody I have talked to sells them. They get them via hook and crook from intel, but actually buy them? never happens. ron

4 10

RE: Debugging the linuxBIOS code
by Colin Hall 12 May '03

12 May '03

Adam, > > My understanding is that the Micro-2000 POST-Probe [5] is > the only one > > that can be powered from 3v3. > > > [5] "POST-Probe ", Micro2000, > <http://micro2000.com/postprobe/index.php> > > call me stupid, but where does it say it is an 3.3V? It doesn't, and this is an important point that I am trying to clarify with their engineers who claim that it will work from 3v3. As I said, if anyone can recommend something better I would love to hear about it. Regards, Colin. ********************************************************************** This footnote confirms that this email message has been swept by MIMEsweeper for the presence of computer viruses. www.mimesweeper.com ********************************************************************** This e-mail transmission is intended for the named addressee only. Its contents are private and confidential and should not be read, copied or disclosed by any other person. If you have received this transmission in error, please notify the sender immediately by e-mail. Opinions, conclusions and other information in this message that do not relate to the official business of my Company shall be understood as neither given nor endorsed by it. ________________________________________________ Internet e-mails are not necessarily secure. Optos plc does not accept responsibility for changes made to this message after it was sent. Copyright Optos plc All rights reserved. No part of this communication may be reproduced without the prior written permission of Optos plc. It is expressly declared that this e-mail does not constitute nor form part of a contract or unilateral obligation.

4 6

Re: Linuxbios + Etherboot + tagged Kernel Image
by Yap Ee Huey 07 May '03

07 May '03

Yes, I am going to use etherboot to load kernel image, but I don't know how to link those files. Bendany told me : "etherboot will init the harddisk, and get the linux kernel from the first partition of your harddisk. so you just put the kernel into your harddisk's first partition and the kernel name must be "kernel". filesystem can be ext2. " But I have multiple partitions on my harddisk, Linux is not on /dev/hda1 , is there any other solutions ? Thanks. >From: ron minnich <rminnich(a)lanl.gov> >To: Yap Ee Huey <yapeehuey(a)hotmail.com> >CC: linuxbios(a)clustermatic.org, <etherboot-users(a)lists.sourceforge.net> >Subject: Re: Linuxbios + Etherboot + tagged Kernel Image >Date: Thu, 24 Apr 2003 08:42:08 -0600 (MDT) > > >one quick question: are you using etherboot to load the kernel image? > >ro > _________________________________________________________________ Using a handphone prepaid card? Reload your credit online! http://www.msn.com.my/reloadredir/default.asp

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Via EPIA
by Russell Gower 06 May '03

06 May '03

Could someone please point me in the right direction. I need to enable wake on Ring for the onboard serial port and/or AC power recovery on a via epia 5000 mainboard. Thanks Russell

2 1

Delay in copying Linuxbios to ram
by Shubhangi Jadhav 06 May '03

06 May '03

Hi, While trying to boot using linuxbios , I get a message " Copying LinuxBIOS to ram " and then the system pauses for 3-4 secs, before printing the next message - "Jumping to Linuxbios" Could someone tell me what causes this delay, does the process of uncompressing and copying linuxbios to RAM take this long? Any suggestions on how to reduce this delay? Here's the log of the debug messages. ***************log********************************* LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, nsuperio 1 handle_superio Pass 0, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 0, Superio w83627hf handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [8086/7124] PCI: 00:1e.0 [8086/2418] PCI: 00:1f.0 [8086/2410] PCI: 00:1f.1 [8086/2411] PCI: 00:1f.2 [8086/2412] PCI: 00:1f.3 [8086/2413] PCI: 00:1f.5 [8086/2415] PCI: 00:1f.6 [8086/2416] PCI: pci_scan_bus for bus 1 PCI: 01:04.0 [10ec/8139] PCI: 01:05.0 [10ec/8139] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:1e.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:1e.0 24 <- [0xfec00000 - 0xfebfffff] bus 1 prefmem PCI: 00:1e.0 20 <- [0xfeb00000 - 0xfebfffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:04.0 10 <- [0x00001000 - 0x000010ff] io PCI: 01:04.0 14 <- [0xfeb00000 - 0xfeb000ff] mem PCI: 01:05.0 10 <- [0x00001400 - 0x000014ff] io PCI: 01:05.0 14 <- [0xfeb01000 - 0xfeb010ff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:1f.1 20 <- [0x000028e0 - 0x000028ef] io PCI: 00:1f.2 20 <- [0x000028c0 - 0x000028df] io PCI: 00:1f.3 20 <- [0x000028f0 - 0x000028ff] io PCI: 00:1f.5 10 <- [0x00002000 - 0x000020ff] io PCI: 00:1f.5 14 <- [0x00002880 - 0x000028bf] io PCI: 00:1f.6 10 <- [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 <- [0x00002800 - 0x0000287f] io ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:1e.0 cmd <- 07 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 00:1f.6 cmd <- 01 PCI: 01:04.0 cmd <- 03 PCI: 01:05.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized DRP0 = 0x9 DIMM0 - size = 64M DIMM1 - size = 0M DRP1 = 0x0 DIMM2 - size = 0M totalram: 64M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000678 pf=0x00000001 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Configuring L2 cache...Not 'GenuineIntel' Processor Enable Cache done. Disabling local apic...done. CPU #0 Initialized ioapic southbridge enabled 180 RTC Init Invalid CMOS LB checksum set power on after power fail Please turn on nvram handle_superio start, nsuperio 1 handle_superio Pass 1, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 1, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call init Enabling com device: 03 iobase = 0x02f8 irq=3 handle_superio Pass 1, done #0 handle_superio done handle_superio start, nsuperio 1 handle_superio Pass 2, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 2, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 2, done #0 handle_superio done Wrote linuxbios table at: 00000500 - 00000664 checksum 7535 Jumping to linuxbiosmain()... Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. January 2000, James Hendricks, Dale Webster, and Ron Minnich. Version 0.1 Regards, Shubhangi

7 15

Hammer Documentation is now Available at AMD's website
by ebiederman＠lnxi.com 06 May '03

06 May '03

So far I have just skimmed the Documentation but it appears that AMD has now publicly published everything needed to do Hammer LinuxBIOS port. No great surprise but it is nice to actually see it ! Yeah! The chaos with the Dual Athlons has finally paid off :) Eric

6 10

low compression of kernel
by Felix Kloeckner 01 May '03

01 May '03

hello, just a simple question: what's the reason for using only a compression level of 3 instead of default or even maximum? 9 works fine for me and give me some additional space for the kernel "makerule linux.bin.gz: linux.bin ;gzip -f -3 linux.bin" in "src/arch/i386/config/make.base", line 39 felix

5 15

Re: ADLO is GO
by Richard Smith 01 May '03

01 May '03

Ok. that fixed it.. ADLO is booting for me. For the list: I had to enable read and write in the shadow memory. I don't think you had to but I enabled the full range from 0c0000 to 0ffffff Adam: I added a macro that does a PCI config space write. Saves you from haveing to do all the calulations. Would you like a diff? It doesn't appear however that my video bios is getting called. I rememember seeing somewhere that I have to enable that? -- Richard A. Smith rsmith(a)bitworks.com

3 6

ADLO Video is up
by Richard Smith 30 Apr '03

30 Apr '03

Adam Sulmicki wrote: > can you just diasable/remove debug patch and see what happen? i actually > never used that patch. Thats what it was. I commented out SERIAL_DEBUG and now I have text on my monitor. Dude this is COOL. Ok... Now. This board is a multi-head board so there are actually 2 69000 on the PCI bus. I also need to init the second chip as well. The way we did this under General software was to activate chip 2. run bios. Deactivate chip 2. Activate chip 1 and then re run the bios. Would I have to do such a thing for BOCHS as well or is there a better way. -- Richard A. Smith rsmith(a)bitworks.com

2 3

ADLO no go
by Richard Smith 30 Apr '03

30 Apr '03

I'm trying to get ADLO up but once it jumps to adlo nothing happens. I've applied the serial-debug patch to ADLO but still no results. Are there any specific memory region options that I need to have enabled /disabled? Heres the snipit from my serial output. Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 Using stream address 0x9c00 37:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 (cleaned up) New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 Loading Segment: addr: 0x0000000007f67368 memsz: 0x0000000000020400 filesz: 0x0000000000020400 Jumping to boot code at 0x7c00 <machine is toast at this point> -- Richard A. Smith rsmith(a)bitworks.com

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coreboot April 2003