On Thu, Aug 22, 2019 at 4:59 AM Matt B <matthewwbradley6(a)gmail.com> wrote:
I believe S3 resume path is PSP assisted. When x86 core reset is deasserted some parts of
the memory controller PHY have already been programmed by PSP or SMU firmwares.
(No PSP present on the G505s)
Perhaps my commentary was not so clear, this was meant in the context
You should consider binaryPI mostly broken for the purpose of S3 suspend/resume.
AMD never got S3 right for open-source AGESA and I think they struggled long to get it
right for amd/stoneyridge.
Does this and the above regarding the PSP mean that S3 is impossible on the G505s
(open-source AGESA), or would otherwise require changes to the AGESA source? (even if
C_ENVIRONMENT_BOOTBLOCK were implemented? If I understand correctly the other two
requirements are already fulfilled?)
Absolutely not! G505s does have working S3 support. We (coreboot
community) got it right while AMD did not. ACPI S3 support is not in
the release requirements. For G505s and other open-source AGESA,
C_ENVIRONMENT_BOOTBLOCK is what is currently lacking. For binaryPI,
like mentioned, POSTCAR_STAGE=y support code is mostly there but the
platform code is landing slowly.
I have been
told that later AGESAv5 firmwares do not have the capability of "MRC cache" to
speed up cold boot as they lack the (x86) code to replay memory training parameters from
Does this apply to the G505s? I presume that it's version of AGESA predates that used
to create the PI binaries.
Different reason why it does apply to G505s; our copy of family15tn
AGESA source was so old the feature was not yet implemented, at least
correctly. For family16kb this feature does work .
0:1st timestamp 1,923
1:start of romstage 1,972 (48)
2:before ram initialization 67,680 (65,707)
3:after ram initialization 2,572,863 (2,505,183)
4:end of romstage 2,584,322 (11,458)
0:1st timestamp 1,924
1:start of romstage 1,973 (48)
2:before ram initialization 67,988 (66,014)
3:after ram initialization 397,508 (329,520)
4:end of romstage 408,894 (11,386)