I believe S3 resume path is PSP assisted. When x86 core reset is deasserted some parts of the memory controller PHY have already been programmed by PSP or SMU firmwares.
(No PSP present on the G505s)
You should consider binaryPI mostly broken for the purpose of S3 suspend/resume.
AMD never got S3 right for open-source AGESA and I think they struggled long to get it right for amd/stoneyridge.
Does this and the above regarding the PSP mean that S3 is impossible on the G505s (open-source AGESA), or would otherwise require changes to the AGESA source? (even if C_ENVIRONMENT_BOOTBLOCK were implemented? If I understand correctly the other two requirements are already fulfilled?)
I have been told that later AGESAv5 firmwares do not have the capability of "MRC cache" to speed up cold boot as they lack the (x86) code to replay memory training parameters from non-volatile memory.
Does this apply to the G505s? I presume that it's version of AGESA predates that used to create the PI binaries.