Re: [coreboot] tiny bootblock problem

[Nils]

Patrick Georgi wrote:
> > Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
> > Cache is setup via MSR registers.
>
> MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
> sure if Geode does it the same way, but MSR doesn't mean "no MTRR".

See attachment for part of page 494 of the GX2 databook.:)

Philip Prindeville wrote:
> Caching is bits 30:29 of CR0.

There are actually a lot more MSR registers for defining cache regions.

Thanks, Nils.

tiny bootblock problem

[Philip Prindeville]

On 1/6/12 3:53 PM, Nils wrote:
> Patrick Georgi wrote:
> > > Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
> > > Cache is setup via MSR registers.
> >
> > MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
> > sure if Geode does it the same way, but MSR doesn't mean "no MTRR".
>
> See attachment for part of page 494 of the GX2 databook.:)
>
> Philip Prindeville wrote:
> > Caching is bits 30:29 of CR0.
>
> There are actually a lot more MSR registers for defining cache regions.
>
> Thanks, Nils.

I think we have a disconnect on what "Not supported" means. :-)