I try to debug coreboot with **spike**. I has apply the **8250 usart patch** to **spike**. But I get from the official website of the code can not pass the test. I found some BUG when I debug this. I want to submit the code but I can't test it. What can i do, who can help me.
I get code from `https://review.coreboot.org/coreboot.git%60
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王翔
安全研究员
广州市腾御安信息科技有限公司
广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024
On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote:
I try to debug coreboot with **spike**. I has apply the **8250 usart patch** to **spike**.
I haven't updated the patches at [1] in a while. Please check if the two patches in [2] work for you if you also apply the following patch to coreboot:
------------------------------------------------------------------------ diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 57647fee1d..26ab630091 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -20,5 +20,5 @@
uintptr_t uart_platform_base(int idx) { - return (uintptr_t) 0x40001000; + return (uintptr_t) 0x02100000; } ------------------------------------------------------------------------
[1]: https://github.com/riscv/riscv-isa-sim/pull/53 [2]: https://github.com/neuschaefer/riscv-isa-sim/commits/uart-update
But I get from the official website of the code can not pass the test. I found some BUG when I debug this.
What did you test? How did it fail?
Regards, Jonathan Neuschäfer
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Jonathan Neuschäfer -
王翔