Elkhart Lake board bring up questions

[Dubravko Moravski | Exor Embedded S.r.l.]

Hello Coreboot,

I work for a company that makes a board containing an Elkhart Lake CPU and we use Coreboot to boot it.

We have started from Intel's document #626123 source files and document #641906 for instructions. Release notes say "This is the main release of the coreboot Boot Loader Proof of Concept for the Elkhart Lake (EHL) series. Date: May 2021; revision: PR 1; description: PR 1 release"
We have already asked Intel for assistance, but they redirected us here.

The final Coreboot binary works, but we are having some issues that so far we were unable to solve on our own.
We are using latest Linux Mint x64 for most of our tests and soon we'll switch to Yocto.

1.  There are roughly about 200 configurable pins on the CPU. We would like to use some as GPIOs. We can configure pin functionalities according to our needs in Coreboot source code (gpio.c, gpio_table[] definition), but Linux doesn't seem to know what to do with GPIO pins: in /sys/class/gpio we only see gpiochip445. To which of the EHL pins does 445 correspond? What should we do to see the rest of the pins? Some comments in the code suggest there can't be more than 32 pins per 'gpiochip'.
 2.  We have enabled CAN controllers in devicetree.cb:
                           device pci 18.1 on           end # Intel Programmable Services Engine CAN0
                           device pci 18.2 on           end # Intel Programmable Services Engine CAN1
... but in Linux we don't see devices 0:18.1 and 0:18.2. What else should we do to enable CAN controllers?
 3.  How do we enable eSPI in Coreboot and how it should be accessible afterwards in Linux? We did:
                           device pci 1f.0 on           end # eSPI Interface
Device 0:1f.0 is visible. How should we access this bus in Linux or declare a device in SSDT table on this bus?
 4.  We have a TPM chip SLB9670 connected to FSPI, CS2.
device pci 1f.5 on           end # PCH SPI (flash & TPM)
... and device 0:1f.5 is visible, but Linux kernel reports it couldn't find any TPM chip. What do we need to do to get it working?
$ dmesg | grep -i tpm
[    0.006614] ACPI: TPM2 0x0000000075AEF4B0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200717)
[    0.006640] ACPI: Reserving TPM2 table memory at [mem 0x75aef4b0-0x75aef4fb]
[    0.771703] ima: No TPM chip found, activating TPM-bypass!
 5.  We can't get audio to work.
device pci 1f.3 on           end # cAVS/HDA
... and device 0:1f.3 is visible. This is output from kernel:
$ dmesg | grep -i hda
[    5.559993] snd_hda_intel 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
[    5.560003] snd_hda_intel 0000:00:1f.3: NHLT table not found
[   66.698806] snd_hda_intel 0000:00:1f.3: couldn't bind with audio component
[   66.731030] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
[   66.731465] snd_hda_intel 0000:00:1f.3: Cannot probe codecs, giving up
We think Linux should see (up to) 3 audio devices: HDMI, DisplayPort and analog codec CS4207.

Thank you in advance for any advice.

Dubravko Moravski
SW engineering
Exor Embedded S.r.l.
p:      [phone]tel:+38%20512455659  m: [phone]tel:+38%205915402413
a:      Slavonska avenija, 50, Zagreb, Croatia, 10000
w:      exorint.comhttps://exorint.com/
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[Paul Menzel]

Dear Dubravko,

Am 07.04.22 um 13:22 schrieb Dubravko Moravski | Exor Embedded S.r.l.:
> I work for a company that makes a board containing an Elkhart Lake
> CPU and we use Coreboot to boot it.

Welcome to coreboot! It’s great to hear, that you use it. A minor note 
in the beginning, that coreboot is officially spelled all lowercase. 
Also, please only send plain text messages to mailing list without JPG 
attachments and HTML parts.
> We have started from Intel's document #626123 source files and
> document #641906 for instructions. Release notes say "This is the
> main release of the coreboot Boot Loader Proof of Concept for the
> Elkhart Lake (EHL) series. Date: May 2021; revision: PR 1;
> description: PR 1 release" We have already asked Intel for
> assistance, but they redirected us here.
>
> The final Coreboot binary works, but we are having some issues that
> so far we were unable to solve on our own. We are using latest Linux
> Mint x64 for most of our tests and soon we'll switch to Yocto.

[…]

I am a little surprised, that Intel asks you to contact the coreboot 
community for their source code dump, which we do not have access to. 
Did you try the code from the upstream master branch? Also, please 
always attach/provide the full logs, and I’d write one message per problem.

Anyway, as you developing a commercial product, I recommend to contract 
support from coreboot consultant companies [1]. Developing FLOSS needs a 
lot of resources, and people making money with it should contribute back 
in some kind of way, and also factor that price into their price offerings.

Kind regards,

Paul

[1]: https://www.coreboot.org/consulting.html

[Zeh, Werner]

Hi Dubravko.
> We have enabled CAN controllers in devicetree.cb:
>                         device pci 18.1 on           end # Intel Programmable Services Engine CAN0
>                         device pci 18.2 on           end # Intel Programmable Services Engine CAN1
>
> ... but in Linux we don't see devices 0:18.1 and 0:18.2. What else should we do to enable CAN controllers?

There is a FSP-S parameter called 'PchPseCanEnable' which controls who (x86 or PSE) owns the CAN controllers. Make sure that you have assigned them to x86 domain.
There is a devictree config for that called 'PseCanOwn' which provides a way to select the ownership on mainboard level.
In addition, make sure device 18.0 (PSE I2C7) is enabled as well as this is the function 0 of the 0x18 device which needs to be enabled to allow Linux to see the other functions of this device.
> How do we enable eSPI in Coreboot and how it should be accessible afterwards in Linux? We did:
>                        device pci 1f.0 on           end # eSPI Interface

Once you did enabled the PCI device you should be able to see it in Linux as well. If this is the case, then you need a PCI driver to handle the controller, just like with all other PCI devices.
> We have a TPM chip SLB9670 connected to FSPI, CS2.
>
> device pci 1f.5 on           end # PCH SPI (flash & TPM)
> ... and device 0:1f.5 is visible, but Linux kernel reports it couldn't find any TPM chip. What do we need to do to get it working?

For your TPM to be visible to the OS you have to attach its driver to the eSPI PCI device in your devicetree as this is the one which actually handles the TPM transactions.
So add the following to your device tree and select the needed TPM Kconfig switches should do the trick:

device pci 1f.0 on          # eSPI Interface
        chip drivers/pc80/tpm
                device pnp 0c31.0 on end
        end
end
> We can't get audio to work.
>
> device pci 1f.3 on           end # cAVS/HDA
> ... and device 0:1f.3 is visible. This is output from kernel:
> $ dmesg | grep -i hda
> [    5.559993] snd_hda_intel 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
> [    5.560003] snd_hda_intel 0000:00:1f.3: NHLT table not found
> [   66.698806] snd_hda_intel 0000:00:1f.3: couldn't bind with audio component
> [   66.731030] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
> [   66.731465] snd_hda_intel 0000:00:1f.3: Cannot probe codecs, giving up
> We think Linux should see (up to) 3 audio devices: HDMI, DisplayPort and analog codec CS4207.

Looks like Linux misses the NHLT ACPI table.
Just have a look for 'NHLT' in the coreboot tree to get an idea what needs to be done for this table to be there.

Werner

From: Dubravko Moravski | Exor Embedded S.r.l. 
Sent: Thursday, April 7, 2022 1:23 PM
To: [e-mail]
Subject: [coreboot] Elkhart Lake board bring up questions

Hello Coreboot,

I work for a company that makes a board containing an Elkhart Lake CPU and we use Coreboot to boot it.

We have started from Intel's document #626123 source files and document #641906 for instructions. Release notes say "This is the main release of the coreboot Boot Loader Proof of Concept for the Elkhart Lake (EHL) series. Date: May 2021; revision: PR 1; description: PR 1 release"
We have already asked Intel for assistance, but they redirected us here.

The final Coreboot binary works, but we are having some issues that so far we were unable to solve on our own.
We are using latest Linux Mint x64 for most of our tests and soon we'll switch to Yocto.

1) There are roughly about 200 configurable pins on the CPU. We would like to use some as GPIOs. We can configure pin functionalities according to our needs in Coreboot source code (gpio.c, gpio_table[] definition), but Linux doesn't seem to know what to do with GPIO pins: in /sys/class/gpio we only see gpiochip445. To which of the EHL pins does 445 correspond? What should we do to see the rest of the pins? Some comments in the code suggest there can't be more than 32 pins per 'gpiochip'.
2) We have enabled CAN controllers in devicetree.cb:
                           device pci 18.1 on           end # Intel Programmable Services Engine CAN0
                           device pci 18.2 on           end # Intel Programmable Services Engine CAN1
... but in Linux we don't see devices 0:18.1 and 0:18.2. What else should we do to enable CAN controllers?
3) How do we enable eSPI in Coreboot and how it should be accessible afterwards in Linux? We did:
                           device pci 1f.0 on           end # eSPI Interface
Device 0:1f.0 is visible. How should we access this bus in Linux or declare a device in SSDT table on this bus?
4) We have a TPM chip SLB9670 connected to FSPI, CS2.
device pci 1f.5 on           end # PCH SPI (flash & TPM)
... and device 0:1f.5 is visible, but Linux kernel reports it couldn't find any TPM chip. What do we need to do to get it working?
$ dmesg | grep -i tpm
[    0.006614] ACPI: TPM2 0x0000000075AEF4B0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200717)
[    0.006640] ACPI: Reserving TPM2 table memory at [mem 0x75aef4b0-0x75aef4fb]
[    0.771703] ima: No TPM chip found, activating TPM-bypass!
5) We can't get audio to work.
device pci 1f.3 on           end # cAVS/HDA
... and device 0:1f.3 is visible. This is output from kernel:
$ dmesg | grep -i hda
[    5.559993] snd_hda_intel 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100
[    5.560003] snd_hda_intel 0000:00:1f.3: NHLT table not found
[   66.698806] snd_hda_intel 0000:00:1f.3: couldn't bind with audio component
[   66.731030] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
[   66.731465] snd_hda_intel 0000:00:1f.3: Cannot probe codecs, giving up
We think Linux should see (up to) 3 audio devices: HDMI, DisplayPort and analog codec CS4207.

Thank you in advance for any advice.

Dubravko Moravski
SW engineering
Exor Embedded S.r.l.
p:
tel:[phone]  m: tel:[phone]
a:
Slavonska avenija, 50, Zagreb, Croatia, 10000
w:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fexorint.co...

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