Hello,
I suspect the RAM on my bay-trail module has no SPD interface. Can Intel's FSP work without SPD ?
I tried to run decode-dimms with vendor's bios and got: No EEPROM found, try loading the eeprom or at24 module
I ran an FSP with debug info and got: C0.D0: SPD not present. C1.D0: SPD not present.
Thank you, Zvika
On 18.02.2019 20:28, Zvi Vered wrote:
Hello,
Hi Zvika,
I suspect the RAM on my bay-trail module has no SPD interface. Can Intel's FSP work without SPD ?
I tried to run decode-dimms with vendor's bios and got: No EEPROM found, try loading the eeprom or at24 module
It looks like You have a platform with soldered down memory. No DIMM slot, am I right?
In this case the is no EEPROM which would hold the SPD data. Typically the SPD should be obtained from hardware vendor/platform vendor.
I ran an FSP with debug info and got: C0.D0: SPD not present. C1.D0: SPD not present.
FSP won't run without SPD, because SPD data is crucial for memory training. It contains timing values, memory hierarchy and other memory characteristics. The memory training process is so complex that it requires the right parameters, which can be retrieved from SPD. The SPD content is highly dependent on memory module design, in Your case the memory chips layout probably, PCB paths length etc.
Thank you, Zvika
Best regards, Michał
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi Michal,
Thank you very much for your reply.
You are right. I have soldered down memory. No dimm slot. In what routine should I configure RAM ? Where can I see a sample code ?
From the RAM vendor I got the following table:
Part Number Byte Number Byte Description Byte Value MT4KTF25664HZ-1G9P1 0 DDR3-CRC RANGE; EEPROM BYTES; BYTES USED 92 MT4KTF25664HZ-1G9P1 1 DDR3-SPD REVISON 13 MT4KTF25664HZ-1G9P1 2 DDR3-DRAM DEVICE TYPE 0B MT4KTF25664HZ-1G9P1 3 DDR3-MODULE TYPE (FORM FACTOR) 3 ....
Is it possible to use FSP but not for RAM setup ? How ? FSP has many features which I want to use. I do not want to write all by myself.
Best regards, Zvika
On Tue, Feb 19, 2019 at 12:27 PM Michal Zygowski michal.zygowski@3mdeb.com wrote:
On 18.02.2019 20:28, Zvi Vered wrote:
Hello,
Hi Zvika,
I suspect the RAM on my bay-trail module has no SPD interface. Can Intel's FSP work without SPD ?
I tried to run decode-dimms with vendor's bios and got: No EEPROM found, try loading the eeprom or at24 module
It looks like You have a platform with soldered down memory. No DIMM slot, am I right?
In this case the is no EEPROM which would hold the SPD data. Typically the SPD should be obtained from hardware vendor/platform vendor.
I ran an FSP with debug info and got: C0.D0: SPD not present. C1.D0: SPD not present.
FSP won't run without SPD, because SPD data is crucial for memory training. It contains timing values, memory hierarchy and other memory characteristics. The memory training process is so complex that it requires the right parameters, which can be retrieved from SPD. The SPD content is highly dependent on memory module design, in Your case the memory chips layout probably, PCB paths length etc.
Thank you, Zvika
Best regards, Michał
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Michał Żygowski Fimrware Engineerhttp://3mdeb.com | @3mdeb_com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On 2/19/19 7:50 PM, Zvi Vered wrote:
Hi Michal,
Thank you very much for your reply.
You are right. I have soldered down memory. No dimm slot. In what routine should I configure RAM ? Where can I see a sample code ?
coreboot has everything prepared for that. What I would do is to look at existing BayTrail platforms supported in coreboot (e.g. Intel Minnow Max), which uses FSP. As it is BayTrail it will surely be FSP1.0.
From the RAM vendor I got the following table:
Part Number Byte Number Byte Description Byte Value MT4KTF25664HZ-1G9P1 0 DDR3-CRC RANGE; EEPROM BYTES; BYTES USED 92 MT4KTF25664HZ-1G9P1 1 DDR3-SPD REVISON 13 MT4KTF25664HZ-1G9P1 2 DDR3-DRAM DEVICE TYPE 0B MT4KTF25664HZ-1G9P1 3 DDR3-MODULE TYPE (FORM FACTOR) 3
....
Is it possible to use FSP but not for RAM setup ? How ? FSP has many features which I want to use. I do not want to write all by myself.
Great that You have found the SPD. AFAIK FSP1.0 has only one entry available (except TempRamInit), i.e. FspInit which initializes memory and silicon. It is inseparable comparing to FSP1.1 or FSP2.0, so everything has to be set right away from the start. FSP will always be used for RAM setup for BayTrail, unless You have a MRC binary. Of course there are some boards that do not need any blob for memory initialization, but this is out of scope of this topic.
Most configuration settings for FSP is defined in mainboard's devicetree.cb file. What You would have to do in the devicetree is to set EnableMemoryDown option and all other memory parameters DIMM* and DRAM* (taken from SPD) as listed here (only example of minnowmax): https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/minnowm...
You don't need to worry much about writing code, since everything is almost in place. Have a look at: src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c and src/drivers/intel/fsp1_0/fsp_util.c
The settings are automatically filled and FspInitApi is called with the parameters You set in devicetree. What You only need is to create a mainboard directory for Your platform and implement few necessary callbacks. First and foremost, coreboot is a framework :)
Best regards, Zvika
Best regards, Michał
Hi Michal,
Your detailed answer is highly appreciated !
The output I got on the console is: ... Memory Down Data Existed : Enabled - Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): 2 - Type (0: DDR3, 1: DDR3L) : 1 - DIMM0 : Disabled - DIMM1 : Disabled - Width : x8 - Density : 2Gbit - BudWidth : 64bit - Rank # : 1 - tCL : 0B - tRPtRCD : 0B - tWR : 0A - tWTR : 05 - tRRD : 04 - tRTP : 05 - tFAW : 14 ....
The file devicetree.cb contains the default settings. Few parameters are override with the code in romstage.c Am I right ?
I comment all the code in romstage.c but the values printed in the console are only partially identical to the ones in devicetree.cb Does it make sense ?
Finally - very basic question - Where is the binary file of the FSP located ? According to default configuration of minnowmax, no path is specified for FSP and microcode. But somehow they are linked in .
Best regards, Zvika
On Tue, Feb 19, 2019 at 9:29 PM Michal Zygowski michal.zygowski@3mdeb.com wrote:
On 2/19/19 7:50 PM, Zvi Vered wrote:
Hi Michal,
Thank you very much for your reply.
You are right. I have soldered down memory. No dimm slot. In what routine should I configure RAM ? Where can I see a sample code ?
coreboot has everything prepared for that. What I would do is to look at existing BayTrail platforms supported in coreboot (e.g. Intel Minnow Max), which uses FSP. As it is BayTrail it will surely be FSP1.0.
From the RAM vendor I got the following table:
Part Number Byte Number Byte Description Byte Value MT4KTF25664HZ-1G9P1 0 DDR3-CRC RANGE; EEPROM BYTES; BYTES USED 92 MT4KTF25664HZ-1G9P1 1 DDR3-SPD REVISON 13 MT4KTF25664HZ-1G9P1 2 DDR3-DRAM DEVICE TYPE 0B MT4KTF25664HZ-1G9P1 3 DDR3-MODULE TYPE (FORM FACTOR) 3 ....
Is it possible to use FSP but not for RAM setup ? How ? FSP has many features which I want to use. I do not want to write all by myself.
Great that You have found the SPD. AFAIK FSP1.0 has only one entry available (except TempRamInit), i.e. FspInit which initializes memory and silicon. It is inseparable comparing to FSP1.1 or FSP2.0, so everything has to be set right away from the start. FSP will always be used for RAM setup for BayTrail, unless You have a MRC binary. Of course there are some boards that do not need any blob for memory initialization, but this is out of scope of this topic.
Most configuration settings for FSP is defined in mainboard's devicetree.cb file. What You would have to do in the devicetree is to set EnableMemoryDown option and all other memory parameters DIMM* and DRAM* (taken from SPD) as listed here (only example of minnowmax):
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/minnowm...
You don't need to worry much about writing code, since everything is almost in place. Have a look at: src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c and src/drivers/intel/fsp1_0/fsp_util.c
The settings are automatically filled and FspInitApi is called with the parameters You set in devicetree. What You only need is to create a mainboard directory for Your platform and implement few necessary callbacks. First and foremost, coreboot is a framework :)
Best regards, Zvika
Best regards, Michał
-- Michał Żygowski Firmware Engineerhttp://3mdeb.com | @3mdeb_com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On 20.02.2019 22:14, Zvi Vered wrote:
Hi Michal,
Hi Zvika,
Your detailed answer is highly appreciated !
The output I got on the console is: ... Memory Down Data Existed : Enabled
- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): 2
- Type (0: DDR3, 1: DDR3L) : 1
- DIMM0 : Disabled
- DIMM1 : Disabled
- Width : x8
- Density : 2Gbit
- BudWidth : 64bit
- Rank # : 1
- tCL : 0B
- tRPtRCD : 0B
- tWR : 0A
- tWTR : 05
- tRRD : 04
- tRTP : 05
- tFAW : 14
....
The file devicetree.cb contains the default settings. Few parameters are override with the code in romstage.c Am I right ?
devicetree.cb can have Your target settings if You wish so. And yes, You can override the values in mainboard's romstage.c in the `romstage_fsp_rt_buffer_callback` function.
I comment all the code in romstage.c but the values printed in the console are only partially identical to the ones in devicetree.cb Does it make sense ?
It depends, coreboot does the default UPD values check.
Finally - very basic question - Where is the binary file of the FSP located ? According to default configuration of minnowmax, no path is specified for FSP and microcode. But somehow they are linked in .
Everything is in the menuconfig Chipset menu and/or Generic Drivers menu. There You can enable inclusion of microcode and FSP binary. When enabled, the base addresses for the blobs pop up in one or both menus.
Some platforms have their minimal configs in the configs directory, but some unfortunately not and one have to go through whole configuration by himself.
Best regards, Zvika
Best regards, Michał
On Tue, Feb 19, 2019 at 9:29 PM Michal Zygowski <michal.zygowski@3mdeb.com mailto:michal.zygowski@3mdeb.com> wrote:
On 2/19/19 7:50 PM, Zvi Vered wrote:Hi Michal, Thank you very much for your reply. You are right. I have soldered down memory. No dimm slot. In what routine should I configure RAM ? Where can I see a sample code ?coreboot has everything prepared for that. What I would do is to look at existing BayTrail platforms supported in coreboot (e.g. Intel Minnow Max), which uses FSP. As it is BayTrail it will surely be FSP1.0.From the RAM vendor I got the following table: Part Number Byte Number Byte Description Byte Value MT4KTF25664HZ-1G9P1 0 DDR3-CRC RANGE; EEPROM BYTES; BYTES USED 92 MT4KTF25664HZ-1G9P1 1 DDR3-SPD REVISON 13 MT4KTF25664HZ-1G9P1 2 DDR3-DRAM DEVICE TYPE 0B MT4KTF25664HZ-1G9P1 3 DDR3-MODULE TYPE (FORM FACTOR) 3 .... Is it possible to use FSP but not for RAM setup ? How ? FSP has many features which I want to use. I do not want to write all by myself.Great that You have found the SPD. AFAIK FSP1.0 has only one entry available (except TempRamInit), i.e. FspInit which initializes memory and silicon. It is inseparable comparing to FSP1.1 or FSP2.0, so everything has to be set right away from the start. FSP will always be used for RAM setup for BayTrail, unless You have a MRC binary. Of course there are some boards that do not need any blob for memory initialization, but this is out of scope of this topic. Most configuration settings for FSP is defined in mainboard's devicetree.cb file. What You would have to do in the devicetree is to set EnableMemoryDown option and all other memory parameters DIMM* and DRAM* (taken from SPD) as listed here (only example of minnowmax): https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/minnowmax/devicetree.cb#L36 You don't need to worry much about writing code, since everything is almost in place. Have a look at: src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c and src/drivers/intel/fsp1_0/fsp_util.c The settings are automatically filled and FspInitApi is called with the parameters You set in devicetree. What You only need is to create a mainboard directory for Your platform and implement few necessary callbacks. First and foremost, coreboot is a framework :)Best regards, ZvikaBest regards, Michał -- Michał Żygowski Firmware Engineer http://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org <mailto:coreboot@coreboot.org> To unsubscribe send an email to coreboot-leave@coreboot.org <mailto:coreboot-leave@coreboot.org>
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Hi Michal,
Thank you very much for your help.
Best regards, Zvika
On Thu, Feb 21, 2019 at 10:17 AM Michal Zygowski michal.zygowski@3mdeb.com wrote:
On 20.02.2019 22:14, Zvi Vered wrote:
Hi Michal,
Hi Zvika,
Your detailed answer is highly appreciated !
The output I got on the console is: ... Memory Down Data Existed : Enabled
- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): 2
- Type (0: DDR3, 1: DDR3L) : 1
- DIMM0 : Disabled
- DIMM1 : Disabled
- Width : x8
- Density : 2Gbit
- BudWidth : 64bit
- Rank # : 1
- tCL : 0B
- tRPtRCD : 0B
- tWR : 0A
- tWTR : 05
- tRRD : 04
- tRTP : 05
- tFAW : 14
....
The file devicetree.cb contains the default settings. Few parameters are override with the code in romstage.c Am I right ?
devicetree.cb can have Your target settings if You wish so. And yes, You can override the values in mainboard's romstage.c in the `romstage_fsp_rt_buffer_callback` function.
I comment all the code in romstage.c but the values printed in the console are only partially identical to the ones in devicetree.cb Does it make sense ?
It depends, coreboot does the default UPD values check.
Finally - very basic question - Where is the binary file of the FSP located ? According to default configuration of minnowmax, no path is specified for FSP and microcode. But somehow they are linked in .
Everything is in the menuconfig Chipset menu and/or Generic Drivers menu. There You can enable inclusion of microcode and FSP binary. When enabled, the base addresses for the blobs pop up in one or both menus.
Some platforms have their minimal configs in the configs directory, but some unfortunately not and one have to go through whole configuration by himself.
Best regards, Zvika
Best regards, Michał
On Tue, Feb 19, 2019 at 9:29 PM Michal Zygowski michal.zygowski@3mdeb.com wrote:
On 2/19/19 7:50 PM, Zvi Vered wrote:
Hi Michal,
Thank you very much for your reply.
You are right. I have soldered down memory. No dimm slot. In what routine should I configure RAM ? Where can I see a sample code ?
coreboot has everything prepared for that. What I would do is to look at existing BayTrail platforms supported in coreboot (e.g. Intel Minnow Max), which uses FSP. As it is BayTrail it will surely be FSP1.0.
From the RAM vendor I got the following table:
Part Number Byte Number Byte Description Byte Value MT4KTF25664HZ-1G9P1 0 DDR3-CRC RANGE; EEPROM BYTES; BYTES USED 92 MT4KTF25664HZ-1G9P1 1 DDR3-SPD REVISON 13 MT4KTF25664HZ-1G9P1 2 DDR3-DRAM DEVICE TYPE 0B MT4KTF25664HZ-1G9P1 3 DDR3-MODULE TYPE (FORM FACTOR) 3 ....
Is it possible to use FSP but not for RAM setup ? How ? FSP has many features which I want to use. I do not want to write all by myself.
Great that You have found the SPD. AFAIK FSP1.0 has only one entry available (except TempRamInit), i.e. FspInit which initializes memory and silicon. It is inseparable comparing to FSP1.1 or FSP2.0, so everything has to be set right away from the start. FSP will always be used for RAM setup for BayTrail, unless You have a MRC binary. Of course there are some boards that do not need any blob for memory initialization, but this is out of scope of this topic.
Most configuration settings for FSP is defined in mainboard's devicetree.cb file. What You would have to do in the devicetree is to set EnableMemoryDown option and all other memory parameters DIMM* and DRAM* (taken from SPD) as listed here (only example of minnowmax):
https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/minnowm...
You don't need to worry much about writing code, since everything is almost in place. Have a look at: src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c and src/drivers/intel/fsp1_0/fsp_util.c
The settings are automatically filled and FspInitApi is called with the parameters You set in devicetree. What You only need is to create a mainboard directory for Your platform and implement few necessary callbacks. First and foremost, coreboot is a framework :)
Best regards, Zvika
Best regards, Michał
-- Michał Żygowski Firmware Engineerhttp://3mdeb.com | @3mdeb_com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Michał Żygowski Firmware Engineerhttp://3mdeb.com | @3mdeb_com
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
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Michal Zygowski -
Zvi Vered