Re: Builds of Google boards fail due to FSP size

[Subrata Banik]

HI Paul and Team,

I guess there is some kind of miscommunication between the usage of FSP
blobs by the Google team for ChromeOS devices that Intel share via their
GitHub repo.

I didn't check. As Subrata explained in his comments[1], Google seems
> to use some sort of customized FSP binary, which is built from an
> internal repository and also stripped. So I was thinking that might be
> the reason for that issue, because related ChromeOS flashmaps are
> optimized for their FSP binary and not for the one from the public
> Intel repo.

Let me clarify, the changes that I have mentioned in my blog post earlier
is done in context of Alder Lake (Brya variant devices) to optimize the FSP
blobs (a post processing of the FSP blobs) but it doesn't mean that we have
optimized the ChromeOS FMD (SPI layout) to take advantage of the optimized
FSP blobs.

Please take a look into the "chromeos.fmd" file history.

https://github.com/coreboot/coreboot/commits/master/src/mainboard/google/bry...

We need to check why the updated FSP blob is breaking the ChromeOS devices
but as mentioned above the FSP binary that we are using from Intel release
source GitHub and we haven't limited the SPI layout to encash those savings
yet.

Let me know if you are looking for some clarification.

Thanks,
Subrata
> From: Felix Singer 
> Date: Wed, Jun 7, 2023 at 4:56 PM
> Subject: [coreboot] Re: Builds of Google boards fail due to FSP size
> To: Paul Menzel ,
>
> Hi Paul,
>
> On Wed, 2023-06-07 at 08:09 +0200, Paul Menzel wrote:
> > Excuse my ignorance. How can all Google boards fail? Aren’t there
> > Intel hardware generations where FSP should not be updated anymore?
>
> I was unclear, sorry. Only the Alderlake boards are affected as it
> seems.
> > Also, how much space is missing? Why did FSP grow that much?
>
> I didn't check. As Subrata explained in his comments[1], Google seems
> to use some sort of customized FSP binary, which is built from an
> internal repository and also stripped. So I was thinking that might be
> the reason for that issue, because related ChromeOS flashmaps are
> optimized for their FSP binary and not for the one from the public
> Intel repo.
> > Could a third option be to ask the FSP folks to provide smaller
> > blobs?
>
> I don't know how feasible that is. From recent discussions about
> releasing FSP binaries, it's even a thing to get *any* FSP binary
> uploaded on the FSP repo.
>
> However, I think the best compromise is the one I wrote in my second
> mail, which is to use only the FSP headers from the repo but not the
> binaries for ChromeOS builds. Customized binaries can still be added by
> the build system or manually.
>
> For the coreboot CI it shouldn't make much difference (probably not
> anything?) because it does only build-tests and there are still enough
> other boards to build-test that part.
>
> Best
>
> Felix
>
> [1] https://review.coreboot.org/c/coreboot/+/74442
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