I've been looking at the work being done here https://github.com/ellyq/coreboot to get coreboot as an alternative to Erying's flaky BIOS. I'm particularly interested in getting S3 suspend working. From what I can see, the motherboard suspends correctly, but doesn't maintain power to the DRAM, so resets when it resumes.
Given Erying won't provided schematics for the motherboard, is there any other way to work out how to "gate" the DRAM power reset signal? I assume it's controlled by a GPIO pin on the PCH/CPU. Are there standard pin assignments for these signals? I see some references to it in the codebase with respect to Lenovo using a different pin.
Thanks, Tim.
Hi Tim,
On 08.06.23 08:59, Timothy Potter wrote:
I've been looking at the work being done here https://github.com/ellyq/coreboot to get coreboot as an alternative to Erying's flaky BIOS. I'm particularly interested in getting S3 suspend working. From what I can see, the motherboard suspends correctly, but doesn't maintain power to the DRAM, so resets when it resumes.
looking at the code, I don't see anything about an embedded controller (EC). Which seems odd for a mobile platform and might be related. If there is anything on the board that acts as an EC (it could even be embedded in the chipset) it might want to be notified when an ACPI- capable OS is started. I would start by investigating ACPI tables of the vendor OS (DSDT + SSDTs), looking for `EmbeddedControl`.
In any case that port will likely need more development, so a reliable external flash setup and console (e.g. serial UART) would be necessary.
Given Erying won't provided schematics for the motherboard, is there any other way to work out how to "gate" the DRAM power reset signal? I assume it's controlled by a GPIO pin on the PCH/CPU. Are there standard pin assignments for these signals? I see some references to it in the codebase with respect to Lenovo using a different pin.
This may be a red herring. The DRAM reset gate was a thing for platforms around/until Ivy Bridge. Starting with Haswell, it vanished from Intel's platform design guide. And the gated signal SM_DRAMRST# was dropped with the introduction of DDR4, it seems.
If it's not about an EC, it could be something similar, though. So as a last resort, I would try the following: Go into S3 with the vendor firmware, flash a coreboot that would dump the GPIO settings as early as possible, resume into coreboot.
Hope this helps, Nico
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Nico Huber -
Timothy Potter