I try to get coreboot working with asrock 880g pro3 board.
First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333?
Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot? ----------------------------------------------------------------------- diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12; - } else { + } else if (rev_id == 0x42) { + rev = REV_SB800_A13; + } + else { die("It is not SB800 or SB810\r\n"); }
diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@
#define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12 - +#define REV_SB800_A13 0x13
#ifdef __PRE_RAM__ void sb800_lpc_port80(void); -------------------------------------------------------------------------
On 07/15/2012 03:50 PM, Roman Elshin wrote:
I try to get coreboot working with asrock 880g pro3 board.
First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333?
Overwrite the MEM_MAX_LOAD_FREQ macro.
Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot?
Yes, but you'd better to use southbridge/amd/cimx/sb800/, please reference mainboard/advansus/a785e-i.
-- Kerry
diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12;
- } else {
- } else if (rev_id == 0x42) {
rev = REV_SB800_A13;- }
else {diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@
#define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12
+#define REV_SB800_A13 0x13
#ifdef __PRE_RAM__ void sb800_lpc_port80(void);
Yes, but you'd better to use southbridge/amd/cimx/sb800/, please reference mainboard/advansus/a785e-i.
Thanks, I was trying that, mach less success here:
coreboot-4.0-2540-g246e84b-dirty Mon Jul 16 21:17:05 MSK 2012 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cf360] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 microcode: rev id (1043) does not match this patch. microcode: Not updated! Fix microcode_updates[] POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() Exit amd_ht_init() POST: 0x35 SB800 - src/southbridge/amd/cimx/sb800/early.c - get_sbdn - Start. SB800 - src/southbridge/amd/cimx/sb800/early.c - get_sbdn - End. cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f24 F3xD8: 03001816 F3xDC: 00006322 POST: 0x36 core0 started: start_other_cores() init node: 00 cores: 03 Start other core - nodeid: 00 cores: 03 POST: 0x37 started ap apicid: * AP 01 timed out:00000001 * AP 02 timed out:00000001 * AP 03 timed out:00000001
POST: 0x38 rs780_early_setup() fam10_optimization() rs780_por_init
Begin FIDVID MSR 0xc0010071 0x30b800a3 0x40035840 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 init_fidvid_bsp_stage1: timed out reading from ap 01 Wait for AP stage 1: ap_apicid = 2 init_fidvid_bsp_stage1: timed out reading from ap 02 Wait for AP stage 1: ap_apicid = 3 init_fidvid_bsp_stage1: timed out reading from ap 03 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 POST: 0x3a End FIDVIDMSR 0xc0010071 0x30b800a3 0x38005840 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET...
Adding call soft_reset() just after rs780_htinit() in romstage.c allow to go further, now it stops just before boot: --------------------------------------------------------------------- ATA controller 1 at 3010/3020/0 (irq 0 dev 88) ATA controller 2 at 3018/3024/0 (irq 0 dev 88) Got ps2 nak (status=51) ata1-0: ST3500410AS ATA-8 Hard-Disk (465 GiBytes) Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0 ebda moved from 9fc00 to 9f800 USB keyboard initialized ehci_wait_td error - status=80000d42 Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Press F12 for boot menu. --------------------------------------------------------------------- Why it may stop and why soft_reset() call may be needed there? If I try to enable internal vga bios the last message are: --------------------------------------------------------------------- In CBFS, ROM address for PCI: 01:05.0 = ffc00778 PCI expansion ROM, signature 0xaa55, INIT size 0xf000, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 9715, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffc00778 to 0xc0000, 0xf000 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... ... Option ROM returned. Devices initialized Detected error on hypertransport link Unknown device path type: 0
HT: Leftover static devices. Check your devicetree.cb POST: 0x24
Unknown device path type: 149613058 Unknown device path type: 0 --------------------------------------------------------------------- Is the problem in devicetree.cb and how create correct devicetree.cb ?
First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333?
Overwrite the MEM_MAX_LOAD_FREQ macro.
This works thanks, but looks like this are not a main problem, Memtest86 + still find a many errors.
Hi
WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors ECC Errs
0:00:03 3840M 0K LxBIOS on off Std 0 6 0
Tst Pass Failing Address Good Bad Err-Bits Count Chan
1 0 000000ef688 - 0.9MB 000ef688 000ef618 00000090 1 1 0 000000ef698 - 0.9MB 000ef698 000ef618 00000080 2 1 0 000000ef6a0 - 0.9MB 000ef6a0 000ef0a0 00000600 3 1 0 000000ef688 - 0.9MB 000ef688 000ef618 00000090 4 1 0 000000ef698 - 0.9MB 000ef698 000ef618 00000080 5 1 0 000000ef6a0 - 0.9MB 000ef6a0 000ef0a0 00000600 6 1 0 000affdc130 - 2815.8MB affdc130 0ffdc130 a0000000 8 1 0 000affdc134 - 2815.8MB affdc134 0ffdc134 a0000000 9
Yes this is somewhat expected. I the memtest86 uses coreboot memory map, but you installed seabios in the meanwhile. The seabios has periodic interrupts/stack hidden there. Try booting the memtest86 payload withoiut seabios and your errors should be done.
I wanted to fix this but not sure how to proceed here.
Thanks Rudolf
Rudolf Marek wrote:
Yes this is somewhat expected. I the memtest86 uses coreboot memory map, but you installed seabios in the meanwhile. The seabios has periodic interrupts/stack hidden there. Try booting the memtest86 payload withoiut seabios and your errors should be done.
I wanted to fix this but not sure how to proceed here.
I guess SeaBIOS needs to rewrite the tables if it allocates some of the free memory.
//Peter
Yes this is somewhat expected. I the memtest86 uses coreboot memory map, but you installed seabios in the meanwhile. The seabios has periodic interrupts/stack hidden there. Try booting the memtest86 payload withoiut seabios and your errors should be done.
Memtest86 hangs just after start in this case.
Yes, but you'd better to use southbridge/amd/cimx/sb800/, please reference mainboard/advansus/a785e-i.
-- Kerry
Hi, I think my problem while using cimx are reset related, looking on log of my experiments with sb800 (where more success), I see that first initialisation always finished by ...WARM RESET..., and starts after it. With cimx it can not start after WARN RESET, (same way as after hard reset button), it stops with zero post code, and can begin initialization only after power off/on sequence. Can one give some direction how to find solution?
Hi, I think my problem while using cimx are reset related, looking on log of my experiments with sb800 (where more success), I see that first initialisation always finished by ...WARM RESET..., and starts after it. With cimx it can not start after WARN RESET, (same way as after hard reset button), it stops with zero post code, and can begin initialization only after power off/on sequence. Can one give some direction how to find solution?
While playing with bit0,bit1 of SB_MISC_REG84, from my mistake, original flash chip (it is winbond w25q32) was programmed by coreboots content. There was used at25df321a (which are able to boot original bios without such problem) for it before. And this problem are gone (only chip replacement was enough).
Dear Roman,
Am Samstag, den 28.07.2012, 15:15 +0400 schrieb Roman Elshin:
Hi, I think my problem while using cimx are reset related, looking on log of my experiments with sb800 (where more success), I see that first initialisation always finished by ...WARM RESET..., and starts after it. With cimx it can not start after WARN RESET, (same way as after hard reset button), it stops with zero post code, and can begin initialization only after power off/on sequence. Can one give some direction how to find solution?
While playing with bit0,bit1 of SB_MISC_REG84, from my mistake, original flash chip (it is winbond w25q32) was programmed by coreboots content. There was used at25df321a (which are able to boot original bios without such problem) for it before. And this problem are gone (only chip replacement was enough).
were you able to make further progress on your ASRock 880G Pro3 [1]?
Currently Sebastian tries to convert the board ASUS M5A88V Evo [2] from the generic coreboot code, which just supports Family 10h processors, to AMD AGESA/CIMx code. Currently he is stuck with SATA problems. So if you have any input/ideas, it would be awesome if you could report back.
Thanks,
Paul
[1] http://www.asrock.com/mb/AMD/880G%20Pro3/ [2] http://www.asus.com/Motherboards/M5A88V_EVO/
Dear Roman,
sorry for digging up this thread.
Am Sonntag, den 15.07.2012, 11:50 +0400 schrieb Roman Elshin:
I try to get coreboot working with asrock 880g pro3 board.
First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333?
Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible to boot from sata. Are sb850 supported by coreboot?
diff -urN a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c --- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14 21:49:54.000000000 +0400 @@ -94,7 +94,10 @@ rev = REV_SB800_A11; } else if (rev_id == 0x41) { rev = REV_SB800_A12;
- } else {
- } else if (rev_id == 0x42) {
rev = REV_SB800_A13;- }
else {diff -urN a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h --- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000 +0400 +++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000 +0400 @@ -48,7 +48,7 @@
#define REV_SB800_A11 0x11 #define REV_SB800_A12 0x12
+#define REV_SB800_A13 0x13
#ifdef __PRE_RAM__ void sb800_lpc_port80(void);
This patch is useful nevertheless. Could you register to Gerrit [1] and push this patch to it? Otherwise could you please reply with your Signed-off-by line so somebody else can upload it?
Thanks,
Paul
-
Paul Menzel -
Peter Stuge -
Roman Elshin -
Rudolf Marek -
shekairui