After some reading on the PCI spec I am sure that enumerating of the PCI devices on my epia board is not working as it should be.
I assume everyone here is using a recent version of the code. As no one other than those of us using the epia board are having problems, I must assume it is a problem with the VIA chipset and not a bug in Linuxbios.
Booting using a current version, I get the following when enumerating the PCI devices (reading resources)
PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io
From a working system using lspci I have the following
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. Unknown device 6010 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at d000 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 d0 00 00 00 00 00 00 00 00 00 00 06 11 10 60
10h - 1Ch above are all 0, so I assume that there are no BASE ADDRESS registers allocated here. One thing I am curious about is that according to the PCI spec (I only have version 2.1) the base address registers start at 10h, so why, in the above , does the IDE controller, and in fact most of the devices on the board use the higher base address registers ?
Another question I have is the fact that 20h contians d001h. The PCI spec does mention that a device may have don't care bits in the base address. So can I assume that, that is the case here ?
Or is there some strange bit shifting going on ?
What confuses me is that on an earlier version (head version 2401) this worked. Comparing the two versions I can see there have been changes to the PCI parts of the code, but nothing to dramatic, and as I have said no one else seems to be having problems.
The EPIA code is more or less the same, just a few text changes in the debug so was it just working by luck before ?
Does anyone have any thoughts on why the enumeration is wrong ?
I guess I am looking at a wrongly configured southbridge chip or northbridge chip.
Ben.
* Ben Hewson ben@hewson-venieri.com [061210 11:04]:
The EPIA code is more or less the same, just a few text changes in the debug so was it just working by luck before ?
Did you use the same compiler in both tries?
S.
Booting using a current version, I get the following when enumerating the PCI devices (reading resources)
PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io
That looks just fine.
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP])
It's in legacy mode, the first four BARs are disabled (it uses legacy I/O 0x1f0 etc. instead, and the legacy IRQs too).
One thing I am curious about is that according to the PCI spec (I only have version 2.1) the base address registers start at 10h, so why, in the above , does the IDE controller, and in fact most of the devices on the board use the higher base address registers ?
Look at http://www.bswd.com/pciide.pdf, it'll take away your confusion hopefully. A device can use any BAR it wants, it is fine to skip 0x10.
Another question I have is the fact that 20h contians d001h. The PCI spec does mention that a device may have don't care bits in the base address. So can I assume that, that is the case here ?
The low few bits are read-only; bits 01 mean it's an I/O BAR. The base address is 0xd000.
What confuses me is that on an earlier version (head version 2401) this worked. Comparing the two versions I can see there have been changes to the PCI parts of the code, but nothing to dramatic, and as I have said no one else seems to be having problems.
Since the code assigned all five BARs, the controller is in non-legacy mode; this means that LinuxBIOS set it up that way, since legacy mode is the boot-up default. Some controllers use legacy IRQs even in non-legacy mode, maybe that's your problem. What exactly isn't working?
Segher
Segher Boessenkool wrote:
Booting using a current version, I get the following when enumerating the PCI devices (reading resources)
PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io
That looks just fine.
00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP])
It's in legacy mode, the first four BARs are disabled (it uses legacy I/O 0x1f0 etc. instead, and the legacy IRQs too).
One thing I am curious about is that according to the PCI spec (I only have version 2.1) the base address registers start at 10h, so why, in the above , does the IDE controller, and in fact most of the devices on the board use the higher base address registers ?
Look at http://www.bswd.com/pciide.pdf, it'll take away your confusion hopefully. A device can use any BAR it wants, it is fine to skip 0x10.
Another question I have is the fact that 20h contians d001h. The PCI spec does mention that a device may have don't care bits in the base address. So can I assume that, that is the case here ?
The low few bits are read-only; bits 01 mean it's an I/O BAR. The base address is 0xd000.
What confuses me is that on an earlier version (head version 2401) this worked. Comparing the two versions I can see there have been changes to the PCI parts of the code, but nothing to dramatic, and as I have said no one else seems to be having problems.
Since the code assigned all five BARs, the controller is in non-legacy mode; this means that LinuxBIOS set it up that way, since legacy mode is the boot-up default. Some controllers use legacy IRQs even in non-legacy mode, maybe that's your problem. What exactly isn't working?
Ok compiling LB for the same target using the same payload (filo), compiled on the same system, the earlier version works, baring the odd system hang. The later versions gets to filo, but it then comes back with
FILO version 0.5 (root@localhost) Sun Nov 12 17:35:53 GMT 2006 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 Detected floating bus No drive detected on IDE channel 0
I have attached the boot output from both versions. There are only a few differences in output, mostly to do with PCI 0.11.1 which is the IDE controller. The non working version seems to see more resources.
Also when it comes to enabling the IDE controller in compatibilty mode (reg 0x42) the non working versions reports it contains 0xc9, the working version reports the same register as 0. According to the datasheet I have on the southbridge the bottom bits 5-0 in that register should be 0. It is if the non working version is looking at the wrong area of memory.
One other thing perhaps you could explain to me, is what exactly is the "pci_routing_fixup" all about ?
Thanks for the link btw.
Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Normal Mon Dec 4 20:57:05 GMT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.2 [1106/3038] disabled PCI: 00:11.3 [1106/3038] disabled PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled PCI: 00:11.5 [1106/3058] disabled PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c PCI: 00:14.0 [1814/0301] enabled PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 01 io PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 01 prefmem PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 01 mem PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00000400 - 0x000004ff] io PCI: 00:12.0 10 * [0x00000800 - 0x000008ff] io PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io PCI: 00:11.1 10 * [0x00000c10 - 0x00000c17] io PCI: 00:11.1 18 * [0x00000c20 - 0x00000c27] io PCI: 00:11.1 14 * [0x00000c30 - 0x00000c33] io PCI: 00:11.1 1c * [0x00000c40 - 0x00000c43] io Root Device compute_allocate_io: base: 00000c44 size: 00000844 align: 8 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0x00000000 - 0x00007fff] mem PCI: 00:12.0 14 * [0x00008000 - 0x000080ff] mem Root Device compute_allocate_mem: base: 00008100 size: 00008100 align: 15 gran: 0 done Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00000844 align: 8 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00001000 - 0x000010ff] io PCI: 00:12.0 10 * [0x00001400 - 0x000014ff] io PCI: 00:11.1 20 * [0x00001800 - 0x0000180f] io PCI: 00:11.1 10 * [0x00001810 - 0x00001817] io PCI: 00:11.1 18 * [0x00001820 - 0x00001827] io PCI: 00:11.1 14 * [0x00001830 - 0x00001833] io PCI: 00:11.1 1c * [0x00001840 - 0x00001843] io Root Device compute_allocate_io: base: 00001844 size: 00000844 align: 8 gran: 0 done Root Device compute_allocate_mem: base: febf0000 size: 00008100 align: 15 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0xfebf0000 - 0xfebf7fff] mem PCI: 00:12.0 14 * [0xfebf8000 - 0xfebf80ff] mem Root Device compute_allocate_mem: base: febf8100 size: 00008100 align: 15 gran: 0 done Root Device assign_resources, bus 0 link: 0 I would set ram size to 0x40000 Kbytes PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:11.1 10 <- [0x0000001810 - 0x0000001817] io PCI: 00:11.1 14 <- [0x0000001830 - 0x0000001833] io PCI: 00:11.1 18 <- [0x0000001820 - 0x0000001827] io PCI: 00:11.1 1c <- [0x0000001840 - 0x0000001843] io PCI: 00:11.1 20 <- [0x0000001800 - 0x000000180f] io PCI: 00:11.6 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00febf8000 - 0x00febf80ff] mem PCI: 00:14.0 10 <- [0x00febf0000 - 0x00febf7fff] mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 147 PCI: 00:11.0 cmd <- 1c7 PCI: 00:11.1 cmd <- 1c1 PCI: 00:11.6 subsystem <- 00/00 PCI: 00:11.6 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 PCI: 00:14.0 cmd <- 142 done. Initializing devices... Root Device init PCI: 00:00.0 init VT8601 random fixup ... PCI: 00:11.0 init vt8231 init IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0000f840 setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x1000 Assigning IRQ 12 to 0:11.3 Readback = 12 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1000 Assigning IRQ 10 to 0:11.5 Readback = 10 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1400 Assigning IRQ 10 to 0:11.6 Readback = 10 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1400 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1c00 setting pci slot Assigning IRQ 5 to 0:14.0 Readback = 5 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c20 pci_routing_fixup: DONE PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.b init PCI: 00:11.1 init ide_init: enabling compatibility IDE addresses enables in reg 0x42 0xc9 enables in reg 0x42 read back as 0x9 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA LAN APIC_CLUSTER: 0 init malloc Enter, size 668, free_mem_ptr 00018538 malloc 0x00018538 Initializing CPU #0 CPU: vendor Centaur device 673 CPU: family 06, model 07, stepping 03 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:14.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b4c checksum 6adf
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
rom_stream: 0xfffc0000 - 0xfffcffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 000187d4 malloc 0x000187d4 New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 (cleaned up) New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 lb: [0x0000000000004000, 0x000000000001c000) malloc Enter, size 32, free_mem_ptr 000187f4 malloc 0x000187f4 New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 (cleaned up) New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 lb: [0x0000000000004000, 0x000000000001c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000020100 filesz: 0x0000000000006168 [ 0x0000000000100000, 0000000000106168, 0x0000000000120100) <- 00000000000000e0 Clearing Segment: addr: 0x0000000000106168 memsz: 0x0000000000019f98 Loading Segment: addr: 0x0000000000120100 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000120100, 0000000000120148, 0x0000000000120148) <- 0000000000006260 Loaded segments verified segments closed down stream Jumping to boot code at 0x1041d8 entry = 0x001041d8 lb_start = 0x00004000 lb_size = 0x00018000 adjust = 0x0ffe4000 buffer = 0x0ffd0000 elf_boot_notes = 0x00013000 adjusted_boot_notes = 0x0fff7000 FILO version 0.5 (root@localhost) Sun Nov 12 17:35:53 GMT 2006 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 Detected floating bus No drive detected on IDE channel 0 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200
Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Normal Fri Nov 10 18:45:42 GMT 2006 booting... Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] ops PCI: 00:00.0 [1106/0601] enabled malloc Enter, size 668, free_mem_ptr 00018000 malloc 0x00018000 Capability: 0x07 @ 0x80 Capability: 0x08 @ 0x80 Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.2 [1106/3038] disabled PCI: 00:11.3 [1106/3038] disabled PCI: 00:11.4 [1106/8235] ops PCI: 00:11.4 [1106/8235] disabled PCI: 00:11.5 [1106/3058] disabled PCI: 00:11.6 [1106/3068] enabled PCI: devfn 0x8f, bad id 0xffffffff PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled PCI: devfn 0x98, bad id 0xffffffff malloc Enter, size 668, free_mem_ptr 0001829c malloc 0x0001829c PCI: 00:14.0 [1814/0301] enabled PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 1 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: devfn 0x88, bad id 0xffffffff PCI: devfn 0x90, bad id 0xffffffff PCI: devfn 0x98, bad id 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=01 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_io: base: 0000f000 size: 00000000 align: 12 gran: 12 done PCI: 00:01.0 1c <- [0x000000f000 - 0x000000efff] bus 1 io PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 24 <- [0x00fff00000 - 0x00ffefffff] bus 1 prefmem PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:01.0 compute_allocate_mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:01.0 20 <- [0x00fff00000 - 0x00ffefffff] bus 1 mem PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00000400 - 0x000004ff] io PCI: 00:12.0 10 * [0x00000800 - 0x000008ff] io PCI: 00:11.1 20 * [0x00000c00 - 0x00000c0f] io Root Device compute_allocate_io: base: 00000c10 size: 00000810 align: 8 gran: 0 done Root Device compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0x00000000 - 0x00007fff] mem PCI: 00:12.0 14 * [0x00008000 - 0x000080ff] mem Root Device compute_allocate_mem: base: 00008100 size: 00008100 align: 15 gran: 0 done Done reading resources. Setting resources... Root Device compute_allocate_io: base: 00001000 size: 00000810 align: 8 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:11.6 10 * [0x00001000 - 0x000010ff] io PCI: 00:12.0 10 * [0x00001400 - 0x000014ff] io PCI: 00:11.1 20 * [0x00001800 - 0x0000180f] io Root Device compute_allocate_io: base: 00001810 size: 00000810 align: 8 gran: 0 done Root Device compute_allocate_mem: base: febf0000 size: 00008100 align: 15 gran: 0 Root Device read_resources bus 0 link: 0 Root Device read_resources bus 0 link: 0 done PCI: 00:14.0 10 * [0xfebf0000 - 0xfebf7fff] mem PCI: 00:12.0 14 * [0xfebf8000 - 0xfebf80ff] mem Root Device compute_allocate_mem: base: febf8100 size: 00008100 align: 15 gran: 0 done Root Device assign_resources, bus 0 link: 0 I would set ram size to 0x40000 Kbytes PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:11.1 20 <- [0x0000001800 - 0x000000180f] io PCI: 00:11.6 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00febf8000 - 0x00febf80ff] mem PCI: 00:14.0 10 <- [0x00febf0000 - 0x00febf7fff] mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 147 PCI: 00:11.0 cmd <- 1c7 PCI: 00:11.1 cmd <- 1c1 PCI: 00:11.6 subsystem <- 00/00 PCI: 00:11.6 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 PCI: 00:14.0 cmd <- 142 done. Initializing devices... Root Device init PCI: 00:00.0 init VT8601 random fixup ... PCI: 00:11.0 init vt8231 init IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum pci_routing_fixup: dev is 0000f720 setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x1000 pci_level_irq: lower order bits are wrong: want 0x0, got 0x10 Assigning IRQ 12 to 0:11.3 Readback = 12 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1000 pci_level_irq: lower order bits are wrong: want 0x0, got 0x10 Assigning IRQ 10 to 0:11.5 Readback = 10 pci_level_irq: current ints are 0x1000 pci_level_irq: try to set ints 0x1400 pci_level_irq: lower order bits are wrong: want 0x4, got 0x14 Assigning IRQ 10 to 0:11.6 Readback = 10 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1400 pci_level_irq: lower order bits are wrong: want 0x4, got 0x14 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 pci_level_irq: current ints are 0x1400 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot Assigning IRQ 5 to 0:14.0 Readback = 5 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c20 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c pci_routing_fixup: DONE PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init PNP: 002e.b init PCI: 00:11.1 init ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 PCI: 00:11.6 init PCI: 00:12.0 init Configuring VIA LAN APIC_CLUSTER: 0 init malloc Enter, size 668, free_mem_ptr 00018538 malloc 0x00018538 Initializing CPU #0 CPU: vendor Centaur device 673 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf DONE variable MTRRs Clear out the extra MTRR's ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf ADDRESS_MASK_HIGH=0xf call enable_var_mtrr() Leave x86_setup_var_mtrrs
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:14.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 done. Moving GDT to 0x500...ok Wrote linuxbios table at: 00000530 - 00000b4c checksum ced0
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
rom_stream: 0xfffc0000 - 0xfffcffff Found ELF candiate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 000187d4 malloc 0x000187d4 New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 (cleaned up) New segment addr 0x100000 size 0x20100 offset 0xe0 filesize 0x6168 lb: [0x0000000000004000, 0x000000000001c000) malloc Enter, size 32, free_mem_ptr 000187f4 malloc 0x000187f4 New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 (cleaned up) New segment addr 0x120100 size 0x48 offset 0x6260 filesize 0x48 lb: [0x0000000000004000, 0x000000000001c000) Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000020100 filesz: 0x0000000000006168 [ 0x0000000000100000, 0000000000106168, 0x0000000000120100) <- 00000000000000e0 Clearing Segment: addr: 0x0000000000106168 memsz: 0x0000000000019f98 Loading Segment: addr: 0x0000000000120100 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x0000000000120100, 0000000000120148, 0x0000000000120148) <- 0000000000006260 Loaded segments verified segments closed down stream Jumping to boot code at 0x1041d8 entry = 0x001041d8 lb_start = 0x00004000 lb_size = 0x00018000 adjust = 0x0ffe4000 buffer = 0x0ffd0000 elf_boot_notes = 0x00012ee0 adjusted_boot_notes = 0x0fff6ee0 FILO version 0.5 (root@localhost) Thu Oct 5 20:44:46 BST 2006 boot: hda1:/kern root=/dev/hda3 console=ttyS0,115200 hda: LBA48 80GB: ST380011A Mounted ext2fs Found Linux version 2.6.15.1 (root@musicbox) #8 PREEMPT Fri Jun 30 20:04:19 BST 2006 bzImage. Loading kernel...
Also when it comes to enabling the IDE controller in compatibilty mode (reg 0x42) the non working versions reports it contains 0xc9, the working version reports the same register as 0.
You need to set the prog-if field in the PCI config space for the controller to 0x8a, not 0x8f, before doing the BAR allocation to get legacy mode. Did you do this?
Segher
Segher Boessenkool wrote:
Also when it comes to enabling the IDE controller in compatibilty mode (reg 0x42) the non working versions reports it contains 0xc9, the working version reports the same register as 0.
You need to set the prog-if field in the PCI config space for the controller to 0x8a, not 0x8f, before doing the BAR allocation to get legacy mode. Did you do this?
Segher
I am not sure about the order of things, however according to the PCI IDE controller document you pointed me to 0x8a is fine as bits 0 & 2 are don't care. Incidentally both working and non working version set the same values.
The biggest change that I can see is that 2 of the elements in the bus structure have changed from unsigned char's to unsigned 16 bit types. Also in all of the pci read/write functions, the where parameter has changed from a char to an int. So my initial thoughts is that one of these changes has had a nasty side effect someplace but I can't find anything as yet.
Apart from those changes the code is mostly the same. Of course something may be causing a condition #define to compile in something different, although I can't see anything different in any of the config files. I am only comparing files that I think are being used, so it is possible that I am missing something.
Anyway I am going to add alot of debug prints to the pci read/write functions in both working and non working versions and then do a file compare to see if anything is different.
It is probably the sort of bug that is so obvious once you see it, but look perfectly ok until then
Ben
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Ben Hewson -
Segher Boessenkool -
Stefan Reinauer