Hello,
I bought the motherboard ASUS KCMA-D8 to set up a coreboot + Qubes OS workstation. However, I don't find a combination of coreboot + CPU + RAM that works. I have also tried the latest libreboot and it works in most cases, but does not provide microcode updates. For test purposes I tried 41xx/42xx/43xx Opterons.
The error message I get in most cases on the serial null-modem port is:
DIMM training FAILED! Restarting system...soft_reset() called!
I following RAM modules has been used:
- M391B1G73BH0-CK0 (8GB PC3L-12800 UDIMM ECC) // NOK - NT8GC72B4NB1NK-CG (8GB PC3PC3-10600 RDIMM ECC) //NOK - HMT325U7BFR8A (2GB PC3-10600 UDIMM ECC ) //OK, see https://www.raptorengineering.com/coreboot/kcma-d8-status.php
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180.
Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I tried many combinations of RAM modules + CPU + coreboot versions (4.6, 4.7, 4.8, 4.9) but get the above "DIMM training FAILED..." error message in most cases. Any ideas or recommendations for RAM modules that are supported so that a workstation with 32GB or better 64GB can be built? Or why libreboot works and coreboot doesn't?
Thank you.
4225 / #005.log (1x NT8GC72B4NB1NK-CG) // NOK ======================================
coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. ..
AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: More than 1 registered DIMM on 1500mV channel; limiting to DDR3-1600 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done
SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done
InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done
AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00000000 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000000 AutoConfig_D: DramConfigLo: 03082000 AutoConfig_D: DramConfigHi: 0f090084 InitDDRPhy: Start InitDDRPhy: Done mct_SetDramConfigHi_D: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_SetDramConfigHi_D: DramConfigHi: 0f090084 * mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done
DCTInit_D: AutoConfig_D Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done
activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done
TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 24000 TrainDQSReceiverEnCyc: ErrStatus 24000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done
DQSTiming_D: Restarting training on algorithm request SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0004 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done AutoCycTiming_D: Start SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2205 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done
phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done activate_spd_rom() for node 00 enable_spd_node0() DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done
activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 2 DIMM 1 RttNom: 2 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000a ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 0 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 0 DIMM 1 RttWr: 0 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 000e ChangeMemClk: Start set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done ChangeMemClk: Done phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done InitPhyCompensation: DCT 0: Start Waiting for predriver calibration to be applied...done! InitPhyCompensation: DCT 0: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttWr: 2 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done DIMM 1 RttNom: 1 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 DIMM 1 RttNom: 1 DIMM 1 RttNom: 1 DIMM 1 RttWr: 2 DIMM 1 RttWr: 2 fam15_receiver_enable_training_seed: using seed: 003f fam15_receiver_enable_training_seed: using seed: 003f TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done
TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted TrainDQSReceiverEnCyc: Status 2205 TrainDQSReceiverEnCyc: TrainErrors 44000 TrainDQSReceiverEnCyc: ErrStatus 44000 TrainDQSReceiverEnCyc: ErrCode 0 TrainDQSReceiverEnCyc: Done
DIMM training FAILED! Restarting system...soft_reset() called!
4180 #002.log (1x NT8GC72B4NB1NK-CG) // OK ==================================== coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting... .. ..
AutoCycTiming_D: Start mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: 1 registered DIMM on 1500mV channel; limiting to DDR3-1333 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2005 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done
SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2005 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent c SPDSetBanks: Status 2005 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff StitchMemory: Status 2005 StitchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done
InterleaveBanks_D: Status 2005 InterleaveBanks_D: ErrStatus 0 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done
AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00090092 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 000000a0 AutoConfig_D: DramConfigLo: 00082100 AutoConfig_D: DramConfigHi: 0f48000b mct_SetDramConfigHi_D: Start mct_SetDramConfigHi_D: DramConfigHi: 1f48010b mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2005 AutoConfig: ErrStatus 0 AutoConfig: ErrCode 0 AutoConfig: Done
DCTInit_D: AutoConfig_D Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done InitPhyCompensation: DCT 0: Start InitPhyCompensation: DCT 0: Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinalInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 1ffffff BottomIO: c00000 Node: 00 base: 03 limit: 23fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:c00000 CPUMemTyping: Bottom32bIO:c00000 CPUMemTyping: Bottom40bIO:2400000 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done activate_spd_rom() for node 00 enable_spd_node0() activate_spd_rom() for node 00 enable_spd_node0() SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start ChangeMemClk: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start mct_PlatformSpec: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done TrainRcvrEn: Status 2205 TrainRcvrEn: ErrStatus 0 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done
TrainDQSRdWrPos: Status 2205 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 0 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming InterleaveNodes_D: Status 2205 InterleaveNodes_D: ErrStatus 0 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done
InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2205 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D ECC enabled on node: 00 DCTMemClr_Sync_D: Start DCTMemClr_Sync_D: Waiting for memory clear to complete..............
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot.
I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot.
On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180.
Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck
On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot.
I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot.
On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180.
Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi guys,
thank you for the valuable feedbacks. As I can see from the git commits, it was mainly Timothy Pearson from Raptor Engineering Inc who worked on the kcma-d8 porting. Libreboot is based on some version of coreboot 4.6. But it seems that after that a number of RAM related commits has been done,like e.g. this:
commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 24 20:33:29 2016 -0500
mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel.
Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS.
Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand noreply@raptorengineeringinc.com Reviewed-by: Martin Roth martinroth@google.com
Can someone confirm that the latest libreboot on the kcma-d8 is stable, so that the effort of the commit 'dichotomy' will be worth it. This means basically to roll back the commits for the kcma-d8 that has been done since the libreboot fork.
Another approach would be to figure out why only very few RAM modules are supported. I can offer test support, but the analysis exceeds my knowledge and skills in this area.
Regards
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Saturday, June 1, 2019 6:29 PM, Mike Banon mikebdp2@gmail.com wrote:
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck
On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot. I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot. On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
The proprietary BIOS and Libreboot are working well. Also a RAM module that is directly recommended at the Raptor Engineering ASUS KCMA-D8 status page (https://www.raptorengineering.com/coreboot/kcma-d8-status.php) - the 1x DIMM HMT325U7BFR8A is working. Anything else I have here is not working and looping with the message:
DIMM training FAILED! Restarting system...soft_reset() called!
I tried RDIMMs and UDIMMs and different KCMA-D8 boards - brand new and also some from fleabay sold from china with revision numbers that are not mentioned anywhere. Got the same results on all the boards.
What RAM modules are you using? ECC / non-ECC? What sizes?
"FYI you need microcode updates with the 43xx CPU otherwise you will have critical security issues"
Yes, that is the reason I want to use coreboot and 43xx is the target platform. Those 41xx are used just for testing.
I also tried coreboot 4.6 (release) but got the above error message. Looks like I have to remove all commits that has been done since the Libreboot fork. I'm surprised that it's so hard because I thought the KCMA-D8 would be better supported and tested.
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Sunday, June 2, 2019 10:45 AM, up6IfzRzvQCyv9AK4XvYirxDa8 up6IfzRzvQCyv9AK4XvYirxDa8@protonmail.com wrote:
Hi guys,
thank you for the valuable feedbacks. As I can see from the git commits, it was mainly Timothy Pearson from Raptor Engineering Inc who worked on the kcma-d8 porting. Libreboot is based on some version of coreboot 4.6. But it seems that after that a number of RAM related commits has been done,like e.g. this:
commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 24 20:33:29 2016 -0500
mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel.
Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS.
Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com
Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>Can someone confirm that the latest libreboot on the kcma-d8 is stable, so that the effort of the commit 'dichotomy' will be worth it. This means basically to roll back the commits for the kcma-d8 that has been done since the libreboot fork.
Another approach would be to figure out why only very few RAM modules are supported. I can offer test support, but the analysis exceeds my knowledge and skills in this area.
Regards
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Saturday, June 1, 2019 6:29 PM, Mike Banon mikebdp2@gmail.com wrote:
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot. I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot. On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi,
I was using four (and later eight) Crucial CT51272BD160BJ (4GB, ECC, unbuffered) for more than a year (with coreboot 4.7 if I remember correctly) with two Opteron 4284. The only issue I have found is that the memory is running at DDR3-1333 instead of DDR3-1600.
Cheers, Matthias
On 04/06/2019 10:53, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
The proprietary BIOS and Libreboot are working well. Also a RAM module that is directly recommended at the Raptor Engineering ASUS KCMA-D8 status page (https://www.raptorengineering.com/coreboot/kcma-d8-status.php) - the 1x DIMM HMT325U7BFR8A is working. Anything else I have here is not working and looping with the message:
DIMM training FAILED! Restarting system...soft_reset() called!
I tried RDIMMs and UDIMMs and different KCMA-D8 boards - brand new and also some from fleabay sold from china with revision numbers that are not mentioned anywhere. Got the same results on all the boards.
What RAM modules are you using? ECC / non-ECC? What sizes?
"FYI you need microcode updates with the 43xx CPU otherwise you will have critical security issues"
Yes, that is the reason I want to use coreboot and 43xx is the target platform. Those 41xx are used just for testing.
I also tried coreboot 4.6 (release) but got the above error message. Looks like I have to remove all commits that has been done since the Libreboot fork. I'm surprised that it's so hard because I thought the KCMA-D8 would be better supported and tested.
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Sunday, June 2, 2019 10:45 AM, up6IfzRzvQCyv9AK4XvYirxDa8 up6IfzRzvQCyv9AK4XvYirxDa8@protonmail.com wrote:
Hi guys,
thank you for the valuable feedbacks. As I can see from the git commits, it was mainly Timothy Pearson from Raptor Engineering Inc who worked on the kcma-d8 porting. Libreboot is based on some version of coreboot 4.6. But it seems that after that a number of RAM related commits has been done,like e.g. this:
commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 24 20:33:29 2016 -0500
mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel.
Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS.
Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com
Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>Can someone confirm that the latest libreboot on the kcma-d8 is stable, so that the effort of the commit 'dichotomy' will be worth it. This means basically to roll back the commits for the kcma-d8 that has been done since the libreboot fork.
Another approach would be to figure out why only very few RAM modules are supported. I can offer test support, but the analysis exceeds my knowledge and skills in this area.
Regards
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Saturday, June 1, 2019 6:29 PM, Mike Banon mikebdp2@gmail.com wrote:
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot. I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot. On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
To avoid having to run a libreboot / ancient version of libreboot, there is a need for commit dichotomy to find out which commit broke the things - and, if you would like it to happen faster, you'll have to do it by yourself. It shouldn't take too much time: even if you'd start with the ancient coreboot 4.1 (Jul 2015) there would be just 14 dichotomy checks: 2^14 = 16384 and there are slightly fewer commits between them
On Tue, Jun 4, 2019 at 1:20 PM up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot coreboot@coreboot.org wrote:
The proprietary BIOS and Libreboot are working well. Also a RAM module that is directly recommended at the Raptor Engineering ASUS KCMA-D8 status page (https://www.raptorengineering.com/coreboot/kcma-d8-status.php) - the 1x DIMM HMT325U7BFR8A is working. Anything else I have here is not working and looping with the message:
DIMM training FAILED! Restarting system...soft_reset() called!
I tried RDIMMs and UDIMMs and different KCMA-D8 boards - brand new and also some from fleabay sold from china with revision numbers that are not mentioned anywhere. Got the same results on all the boards.
What RAM modules are you using? ECC / non-ECC? What sizes?
"FYI you need microcode updates with the 43xx CPU otherwise you will have critical security issues"
Yes, that is the reason I want to use coreboot and 43xx is the target platform. Those 41xx are used just for testing.
I also tried coreboot 4.6 (release) but got the above error message. Looks like I have to remove all commits that has been done since the Libreboot fork. I'm surprised that it's so hard because I thought the KCMA-D8 would be better supported and tested.
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Sunday, June 2, 2019 10:45 AM, up6IfzRzvQCyv9AK4XvYirxDa8 up6IfzRzvQCyv9AK4XvYirxDa8@protonmail.com wrote:
Hi guys,
thank you for the valuable feedbacks. As I can see from the git commits, it was mainly Timothy Pearson from Raptor Engineering Inc who worked on the kcma-d8 porting. Libreboot is based on some version of coreboot 4.6. But it seems that after that a number of RAM related commits has been done,like e.g. this:
commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 24 20:33:29 2016 -0500
mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage
The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel.
Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS.
Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com
Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>Can someone confirm that the latest libreboot on the kcma-d8 is stable, so that the effort of the commit 'dichotomy' will be worth it. This means basically to roll back the commits for the kcma-d8 that has been done since the libreboot fork.
Another approach would be to figure out why only very few RAM modules are supported. I can offer test support, but the analysis exceeds my knowledge and skills in this area.
Regards
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Saturday, June 1, 2019 6:29 PM, Mike Banon mikebdp2@gmail.com wrote:
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot. I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot. On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Ok, it seems that there are some general issues with the RAM compability. Libreboot seems to have some code that has less issues with some RAM sticks, but the stability has yet to be confirmed. For example, I discovered a scenario where the size of the RAM was detected incorrectly. The question now is whether it is worth investing time in the KCMA-D8 or to say that it is no longer supported. Are there alternatives for a secure workstation?
I am ready to put a board aside for regression testing and test different versions of coreboot for lets say the next 1-2 years. I have to organize an eeprom emulator before to save myself the permanent replugging and flashing of the eeprom. But I cannot solve the fundamental 'DIMM training FAILED! Restarting system...soft_reset() called!' problem. I lack the time and knowledge of the topic. But I can do the commit dichotomy, though. Anybody wants to join in?
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Wednesday, June 5, 2019 1:33 PM, Mike Banon mikebdp2@gmail.com wrote:
To avoid having to run a libreboot / ancient version of libreboot, there is a need for commit dichotomy to find out which commit broke the things - and, if you would like it to happen faster, you'll have to do it by yourself. It shouldn't take too much time: even if you'd start with the ancient coreboot 4.1 (Jul 2015) there would be just 14 dichotomy checks: 2^14 = 16384 and there are slightly fewer commits between them
On Tue, Jun 4, 2019 at 1:20 PM up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot coreboot@coreboot.org wrote:
The proprietary BIOS and Libreboot are working well. Also a RAM module that is directly recommended at the Raptor Engineering ASUS KCMA-D8 status page (https://www.raptorengineering.com/coreboot/kcma-d8-status.php) - the 1x DIMM HMT325U7BFR8A is working. Anything else I have here is not working and looping with the message: DIMM training FAILED! Restarting system...soft_reset() called! I tried RDIMMs and UDIMMs and different KCMA-D8 boards - brand new and also some from fleabay sold from china with revision numbers that are not mentioned anywhere. Got the same results on all the boards. What RAM modules are you using? ECC / non-ECC? What sizes? "FYI you need microcode updates with the 43xx CPU otherwise you will have critical security issues" Yes, that is the reason I want to use coreboot and 43xx is the target platform. Those 41xx are used just for testing. I also tried coreboot 4.6 (release) but got the above error message. Looks like I have to remove all commits that has been done since the Libreboot fork. I'm surprised that it's so hard because I thought the KCMA-D8 would be better supported and tested. ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Sunday, June 2, 2019 10:45 AM, up6IfzRzvQCyv9AK4XvYirxDa8 up6IfzRzvQCyv9AK4XvYirxDa8@protonmail.com wrote:
Hi guys, thank you for the valuable feedbacks. As I can see from the git commits, it was mainly Timothy Pearson from Raptor Engineering Inc who worked on the kcma-d8 porting. Libreboot is based on some version of coreboot 4.6. But it seems that after that a number of RAM related commits has been done,like e.g. this: commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 24 20:33:29 2016 -0500 mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel. Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS. Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com
Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>Can someone confirm that the latest libreboot on the kcma-d8 is stable, so that the effort of the commit 'dichotomy' will be worth it. This means basically to roll back the commits for the kcma-d8 that has been done since the libreboot fork. Another approach would be to figure out why only very few RAM modules are supported. I can offer test support, but the analysis exceeds my knowledge and skills in this area. Regards ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On Saturday, June 1, 2019 6:29 PM, Mike Banon mikebdp2@gmail.com wrote:
Why libreboot works and coreboot doesn't?
Libreboot is some older version of coreboot where all the blobs have been removed. If something works at libreboot but doesn't work at coreboot, most likely that means there was a breaking commit at coreboot which came later than a libreboot release (and, like the rest of new commits, this breaking commit is going to be inherited by libreboot in its' next release). When you encounter such a situation, you should do a commit dichotomy to find out which commit broke the things and report it, so that maybe it would be reverted or improved and then the things should become working for you in the latest coreboot master. Good luck On Sat, Jun 1, 2019 at 9:28 AM Sean Lynn Rhone espionage724@posteo.net wrote:
For non-ECC modules on the KCMA-D8, I found that Samsung M378B5273CH0- CK0, Micron 16JTF25664AZ-1G4F1, and Nanya NT2GC64B88B0NF-CG work with Coreboot. I also had SK Hynix HMT151R7BFR4C-H9 which didn't work with Coreboot, but worked on Libreboot. Samsung M393B5270CH0-CH9 also doesn't work with Coreboot. On Fri, 2019-05-31 at 10:00 +0000, up6IfzRzvQCyv9AK4XvYirxDa8 via coreboot wrote:
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180. Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I t
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
There were limited information regarding memory compatibility with KCMA-D8.
On the other hand, there were more information for KGPE-D16 regarding memory compatibility, and it seems the good RDIMM sticks for that board are mostly from either Micron or Kingston. There are few entries about Samsung and Hynix ones (like the ones I currently have, which don't work with coreboot).
Have anyone tested this board with latest coreboot and with either Micron or Kingston RDIMM sticks? I'm yet to rule out the possibility that Samsung or Hynix ones are generally not as compatible with coreboot as with Micron or Kingston ones.
Samsung "M393B5270CH0-CH9" nor SK Hynix "HMT151R7BFR4C-H9" work with the Coreboot 4.9; I'm not sure on a specific error message; the motherboard just didn't POST with those sticks.
The SK Hynix "HMT151R7BFR4C-H9" sticks worked with Libreboot 20160907 however.
Nanya "NT2GC64B88B0NF-CG", Micron "16JTF25664AZ-1G4F1", and Samsung "M378B5273CH0-CK0" worked fine with the Coreboot 4.9 though (the Samsung M378B5273CH0-CK0 sticks still working fine with CB compiled a few days ago).
On Fri, 2019-07-12 at 12:27 +0000, ragnaros@tenebr.is wrote:
There were limited information regarding memory compatibility with KCMA-D8.
On the other hand, there were more information for KGPE-D16 regarding memory compatibility, and it seems the good RDIMM sticks for that board are mostly from either Micron or Kingston. There are few entries about Samsung and Hynix ones (like the ones I currently have, which don't work with coreboot).
Have anyone tested this board with latest coreboot and with either Micron or Kingston RDIMM sticks? I'm yet to rule out the possibility that Samsung or Hynix ones are generally not as compatible with coreboot as with Micron or Kingston ones. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
I planned to test coreboot on this board as well, and I'm having the same problem (compiled from latest source).
The sticks I currently have are 16GB VLP ones. I've some M392B2G70DM0-YK0, and a few HMT42GR7AFR4A-PB. None worked with this board using coreboot, giving out similar "DIMM training failed" message on the serial console output.
All those RAM sticks work on stock BIOS. Just that the board would run them at 1066MHz if all 8 slots are populated (M392B2G70DM0-YK0 for example). Not sure if this is due to incompatibility or is a chipset limitation (manually setting it to 1600MHz in stock BIOS has no effect if using 8 sticks). If only using 4 sticks (which makes 64GB) with stock BIOS, the memory can correctly operate at 1600MHz. Still, none of the combinations (2, 4, 8 sticks) worked with coreboot.
Is there a way to manually force memory clock and timing configuration (such as 1066MHz) for some in-depth testing? On the other hand, I might need to test libreboot to see if it makes a difference, and check for nearby coreboot commits to look for a starting point for bisection.
I run v4.6 and use random ram combos I got off of fleabay without issue on my various opteron boards it might be something else - does the propriatary BIOS have an issue with them?
FYI you need microcode updates with the 43xx CPU otherwise you will have critical security issues, microcode updates may be wanted for spectre anyway. With libreboot you can use the OS early loading mechanism.
41xx CPU's don't work well and are very slow, they lack IOMMU code so I suggest not using them and of course then you would not be able to use qubes due to no IOMMU.
4386 is the best cpu available and the only one that can play games at a satisfactory FPS.
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