Hello,
I bought the motherboard ASUS KCMA-D8 to set up a coreboot + Qubes OS workstation. However, I don't find a combination of coreboot + CPU + RAM that works. I have also tried the latest libreboot and it works in most cases, but does not provide microcode updates. For test purposes I tried 41xx/42xx/43xx Opterons.
The error message I get in most cases on the serial null-modem port is:
DIMM training FAILED! Restarting system...soft_reset() called!
I following RAM modules has been used:
- M391B1G73BH0-CK0 (8GB PC3L-12800 UDIMM ECC) // NOK
- NT8GC72B4NB1NK-CG (8GB PC3PC3-10600 RDIMM ECC) //NOK
There are also differences between 42xx and 42xx/43xx. Below a logfile of coreboot 4.9 with 4225 and 4180.
Test with 4365 + coreboot 4.9 and 1x M391B1G73BH0-CK0 in the Slot A2 and 1x CPU. The same configuration but with the HMT325U7BFR8A (recommended by raptorengineering.com) works. I tried many combinations of RAM modules + CPU + coreboot versions (4.6, 4.7, 4.8, 4.9) but get the above "DIMM training FAILED..." error message in most cases. Any ideas or recommendations for RAM modules that are supported so that a workstation with 32GB or better 64GB can be built? Or why libreboot works and coreboot doesn't?
Thank you.
4225 / #005.log (1x NT8GC72B4NB1NK-CG) // NOK
======================================
coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting...
..
..
AutoCycTiming_D: Start
mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected
mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected
mct_MaxLoadFreq: More than 1 registered DIMM on 1500mV channel; limiting to DDR3-1600
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 6
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00000000
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 00000000
AutoConfig_D: DramConfigLo: 03082000
AutoConfig_D: DramConfigHi: 0f090084
InitDDRPhy: Start
InitDDRPhy: Done
mct_SetDramConfigHi_D: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
mct_SetDramConfigHi_D: DramConfigHi: 0f090084
*
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 1ffffff BottomIO: c00000
Node: 00 base: 03 limit: 23fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 24000
TrainDQSReceiverEnCyc: ErrStatus 24000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done
DQSTiming_D: Restarting training on algorithm request
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0004
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
AutoCycTiming_D: Start
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2205
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
activate_spd_rom() for node 00
enable_spd_node0()
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 2
DIMM 1 RttNom: 2
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000a
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 0
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 0
DIMM 1 RttWr: 0
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 000e
ChangeMemClk: Start
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
ChangeMemClk: Done
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
InitPhyCompensation: DCT 0: Start
Waiting for predriver calibration to be applied...done!
InitPhyCompensation: DCT 0: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
DIMM 1 RttWr: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttWr: 2
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
DIMM 1 RttNom: 1
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
DIMM 1 RttNom: 1
DIMM 1 RttNom: 1
DIMM 1 RttWr: 2
DIMM 1 RttWr: 2
fam15_receiver_enable_training_seed: using seed: 003f
fam15_receiver_enable_training_seed: using seed: 003f
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSReceiverEnCyc_D_Fam15: lane 0 failed to train! Training for receiver 2 on DCT 0 aborted
TrainDQSReceiverEnCyc: Status 2205
TrainDQSReceiverEnCyc: TrainErrors 44000
TrainDQSReceiverEnCyc: ErrStatus 44000
TrainDQSReceiverEnCyc: ErrCode 0
TrainDQSReceiverEnCyc: Done
DIMM training FAILED! Restarting system...soft_reset() called!
4180 #002.log (1x NT8GC72B4NB1NK-CG) // OK
====================================
coreboot-4.9 Wed Dec 19 18:05:51 UTC 2018 romstage starting...
..
..
AutoCycTiming_D: Start
mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected
mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected
mct_MaxLoadFreq: 1 registered DIMM on 1500mV channel; limiting to DDR3-1333
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 6
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2005
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2005
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent c
SPDSetBanks: Status 2005
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1ffffff
StitchMemory: Status 2005
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 2005
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 00002a06
AutoConfig_D: DramTimingLo: 00090092
AutoConfig_D: DramConfigMisc: 00000000
AutoConfig_D: DramConfigMisc2: 000000a0
AutoConfig_D: DramConfigLo: 00082100
AutoConfig_D: DramConfigHi: 0f48000b
mct_SetDramConfigHi_D: Start
mct_SetDramConfigHi_D: DramConfigHi: 1f48010b
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2005
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
InitPhyCompensation: DCT 0: Start
InitPhyCompensation: DCT 0: Done
DCTInit_D: PlatformSpec_D Done
DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 1ffffff BottomIO: c00000
Node: 00 base: 03 limit: 23fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:c00000
CPUMemTyping: Bottom32bIO:c00000
CPUMemTyping: Bottom40bIO:2400000
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
activate_spd_rom() for node 00
enable_spd_node0()
activate_spd_rom() for node 00
enable_spd_node0()
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
ChangeMemClk: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
mct_PlatformSpec: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
TrainRcvrEn: Status 2205
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 2205
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 2205
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 2205
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
ECC enabled on node: 00
DCTMemClr_Sync_D: Start
DCTMemClr_Sync_D: Waiting for memory clear to complete..............