Hi,
I added my new board to mainboards and successfully compile with northbridge i855pm and i82801dbm southbridge.
After flashing and reboot I get beep beep beep 2 times per second. And there is nothing to see on serial output.
I know, that the i855pm is not fully supported and I'm waiting for the patches from Joe, but I thought the serial console may work without it.
Maybe someone is willing to check my config so far. The most stuff is stolen from digitallogic/adl855pc directory.
It would be nice to get the serial console to work in the first step, so I can see what is wrong with the other stuff.
I've uploaded a tar.gz to:
http://www.bloms.de/download/commel_lv671.tar.gz
It is only 9K big ;)
Thank you for your help.
Hello,
Here is a copy of the change log that I have made to the i82801db. I am still working on my northbridge and have not been able to test it. Can someone make the changes and test for me?
/* * This Southbridge needed some fixing up. * March 03, 2007 */
chip.h --------- changed #define ICH5R_GPIO_USE_MASK 0x03 to #define ICH4_GPIO_USE_MASK 0x03 changed #define ICH5R_GPIO_USE_DEFAULT 0x00 to #define ICH4_GPIO_USE_DEFAULT 0x00 changed #define ICH5R_GPIO_USE_AS_NATIVE 0x01 to #define ICH4_GPIO_USE_AS_NATIVE 0x01 changed #define ICH5R_GPIO_USE_AS_GPIO 0x02 to #define ICH4_GPIO_USE_AS_GPIO 0x02
changed #define ICH5R_GPIO_SEL_MASK 0x0c to #define ICH4_GPIO_SEL_MASK 0x0c changed #define ICH5R_GPIO_SEL_DEFAULT 0x00 to #define ICH4_GPIO_SEL_DEFAULT 0x00 changed #define ICH5R_GPIO_SEL_OUTPUT 0x04 to #define ICH4_GPIO_SEL_OUTPUT 0x04 changed #define ICH5R_GPIO_SEL_INPUT 0x08 to #define ICH4_GPIO_SEL_INPUT 0x08
changed #define ICH5R_GPIO_LVL_MASK 0x30 to #define ICH4_GPIO_LVL_MASK 0x30 changed #define ICH5R_GPIO_LVL_DEFAULT 0x00 to #define ICH4_GPIO_LVL_DEFAULT 0x00 changed #define ICH5R_GPIO_LVL_LOW 0x10 to #define ICH4_GPIO_LVL_LOW 0x10 changed #define ICH5R_GPIO_LVL_HIGH 0x20 to #define ICH4_GPIO_LVL_HIGH 0x20 changed #define ICH5R_GPIO_LVL_BLINK 0x30 to #define ICH4_GPIO_LVL_BLINK 0x30
changed #define ICH5R_GPIO_INV_MASK 0xc0 to #define ICH4_GPIO_INV_MASK 0xc0 changed #define ICH5R_GPIO_INV_DEFAULT 0x00 to #define ICH4_GPIO_INV_DEFAULT 0x00 changed #define ICH5R_GPIO_INV_OFF 0x40 to #define ICH4_GPIO_INV_OFF 0x40 changed #define ICH5R_GPIO_INV_ON 0x80 to #define ICH4_GPIO_INV_ON 0x80
i82801db_ac97.c --------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO, to .device = PCI_DEVICE_ID_INTEL_82801DB_5, changed .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM, to .device = PCI_DEVICE_ID_INTEL_82801DB_6,
i82801db_ehci.c --------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI, to .device = PCI_DEVICE_ID_INTEL_82801DB_13,
i82801db_ide.c --------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_IDE, to .device = PCI_DEVICE_ID_INTEL_82801DB_11,
i82801db_lpc.c --------------- changed switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) { to switch(config->gpio[i] & ICH4_GPIO_USE_MASK) { changed case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break; to case ICH4_GPIO_USE_AS_NATIVE: val = 0; break; changed case ICH5R_GPIO_USE_AS_GPIO: val = 1; break; to case ICH4_GPIO_USE_AS_GPIO: val = 1; break; changed switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) { to switch(config->gpio[i] & ICH4_GPIO_SEL_MASK) { changed case ICH5R_GPIO_SEL_OUTPUT: val = 0; break; to case ICH4_GPIO_SEL_OUTPUT: val = 0; break; changed case ICH5R_GPIO_SEL_INPUT: val = 1; break; to case ICH4_GPIO_SEL_INPUT: val = 1; break; changed switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) { to switch(config->gpio[i] & ICH4_GPIO_LVL_MASK) { changed case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break; to case ICH4_GPIO_LVL_LOW: val = 0; blink = 0; break; changed case ICH5R_GPIO_LVL_HIGH: val = 1; blink = 0; break; to case ICH4_GPIO_LVL_HIGH: val = 1; blink = 0; break; changed case ICH5R_GPIO_LVL_BLINK: val = 1; blink = 1; break; to case ICH4_GPIO_LVL_BLINK: val = 1; blink = 1; break; changed switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) { to switch(config->gpio[i] & ICH4_GPIO_INV_MASK) { changed case ICH5R_GPIO_INV_OFF: val = 0; break; to case ICH4_GPIO_INV_OFF: val = 0; break; changed case ICH5R_GPIO_INV_ON: val = 1; break; to case ICH4_GPIO_INV_ON: val = 1; break; changed .device = PCI_DEVICE_ID_INTEL_82801DB_ISA, to .device = PCI_DEVICE_ID_INTEL_82801DB_0,
i82801db_pci.c -------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_PCI, to .device = 0x244e,
i82801db_smbus.c --------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_SMB, to .device = PCI_DEVICE_ID_INTEL_82801DB_3,
i82801db_uhci.c --------------- changed .device = PCI_DEVICE_ID_INTEL_82801DB_USB0, to .device = PCI_DEVICE_ID_INTEL_82801DB_2, changed .device = PCI_DEVICE_ID_INTEL_82801DB_USB1, to .device = PCI_DEVICE_ID_INTEL_82801DB_4, changed .device = PCI_DEVICE_ID_INTEL_82801DB_USB2, to .device = PCI_DEVICE_ID_INTEL_82801DB_7,
i82801db_watchdog.c --------------- changed /* turn off the ICH5 watchdog */ to /* turn off the ICH4 watchdog */ changed printk_debug("Watchdog ICH5 disabled\r\n"); to printk_debug("Watchdog ICH4 disabled\r\n");
ADDED NIC SUPPORT
Added file: i82801db_nic.c
Added this line to Config.lb: driver i82801db_nic.o
Thanks - Joe
Quoting Dieter Bloms dieter@bloms.de:
Hi,
I added my new board to mainboards and successfully compile with northbridge i855pm and i82801dbm southbridge.
After flashing and reboot I get beep beep beep 2 times per second. And there is nothing to see on serial output.
I know, that the i855pm is not fully supported and I'm waiting for the patches from Joe, but I thought the serial console may work without it.
Maybe someone is willing to check my config so far. The most stuff is stolen from digitallogic/adl855pc directory.
It would be nice to get the serial console to work in the first step, so I can see what is wrong with the other stuff.
I've uploaded a tar.gz to:
http://www.bloms.de/download/commel_lv671.tar.gz
It is only 9K big ;)
Thank you for your help.
-- Gruß
Dieter
-- I do not get viruses because I do not use MS software. If you use Outlook then please do not put my email address in your address-book so that WHEN you get a virus it won't use my address in the From field.
Hi,
On Thu, May 31, joe@smittys.pointclark.net wrote:
Here is a copy of the change log that I have made to the i82801db. I am still working on my northbridge and have not been able to test it. Can someone make the changes and test for me?
it does compile, but I can not see anything on the serial console. So I think there is something wrong with my config, because about 5 seconds after power on it beeps and beeps and beeps .... two time per second.
I don't know where I have to look now :(
Quoting Dieter Bloms dieter@bloms.de:
Hi,
On Thu, May 31, joe@smittys.pointclark.net wrote:
Here is a copy of the change log that I have made to the i82801db. I am still working on my northbridge and have not been able to test it. Can someone make the changes and test for me?
it does compile, but I can not see anything on the serial console. So I think there is something wrong with my config, because about 5 seconds after power on it beeps and beeps and beeps .... two time per second.
I don't know where I have to look now :(
-- Gruß
Dieter
--
Dieter, Sounds like maybe the superio is not quite working. What kind of chip is it?
Thanks - Joe
Hi,
On Fri, Jun 01, joe@smittys.pointclark.net wrote:
Quoting Dieter Bloms dieter@bloms.de:
Sounds like maybe the superio is not quite working. What kind of chip is it?
it is a winbond W83627HF-AW
Hi,
On Fri, Jun 01, joe@smittys.pointclark.net wrote:
Quoting Dieter Bloms dieter@bloms.de:
Sounds like maybe the superio is not quite working. What kind of chip is it?
it is a winbond W83627HF-AW
Hmm, on the LB website there is a big ? next to the winbond W83627HF, Has anyone else had sucess wih this chip?
Thanks - Joe
On Sat, Jun 02, 2007 at 10:17:21AM -0400, joe@smittys.pointclark.net wrote:
it is a winbond W83627HF-AW
Hmm, on the LB website there is a big ? next to the winbond W83627HF, Has anyone else had sucess wih this chip?
I'm pretty confident that it should work, haven't tried it myself though.
Uwe.
Uwe Hermann wrote:
On Sat, Jun 02, 2007 at 10:17:21AM -0400, joe@smittys.pointclark.net wrote:
it is a winbond W83627HF-AW
Hmm, on the LB website there is a big ? next to the winbond W83627HF, Has anyone else had sucess wih this chip?
I'm pretty confident that it should work, haven't tried it myself though.
Uwe.
The W83627HF code works for me. I have 2 out of 3 platforms that use it working. The third platform has a problem on the serial lines. I am 99% sure that this is a hardware issue. I think that serial power supply is out of spec.
Marc
Hi,
The W83627HF code works for me. I have 2 out of 3 platforms that use it working. The third platform has a problem on the serial lines. I am 99% sure that this is a hardware issue. I think that serial power supply is out of spec.
the serial console works, when I boot linux. I think I made a mistake while write the Config.lb or auto.c file.
When should I see anything on the console ? Must all chips already be up, so the northbridge i855gm may be the problem, or is the winbond the only chip, which should be up to the anything on the console ?
I don't know where to search now.
* Dieter Bloms dieter@bloms.de [070604 19:36]:
When should I see anything on the console ? Must all chips already be up, so the northbridge i855gm may be the problem, or is the winbond the only chip, which should be up to the anything on the console ?
Is your target using the correct superio driver in auto.c? It's not enough to set it in Config.lb (unfortunately)
Is the SuperIO maybe listening on 4e instead of 2e?
Hi Stefan,
On Mon, Jun 04, Stefan Reinauer wrote:
- Dieter Bloms dieter@bloms.de [070604 19:36]:
When should I see anything on the console ? Must all chips already be up, so the northbridge i855gm may be the problem, or is the winbond the only chip, which should be up to the anything on the console ?
Is your target using the correct superio driver in auto.c? It's not enough to set it in Config.lb (unfortunately)
for now my auto.c looks like:
--snip-- #define ASSEMBLY 1 #define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <arch/hlt.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h"
#include "superio/winbond/w83627hf/w83627hf.h" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void main(unsigned long bist) { /* Setup the console */ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); print_err("Hello\n"); } --snip--
Is the SuperIO maybe listening on 4e instead of 2e?
where can I see where the superio is listening on ?
I've changed the address from 2e to 4e in auto.c and Config.lb, but it didn't change anything.
* Dieter Bloms dieter@bloms.de [070604 23:42]:
#include "superio/winbond/w83627hf/w83627hf.h" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
^^^^
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
Is the SuperIO maybe listening on 4e instead of 2e?
where can I see where the superio is listening on ?
Is your SuperIO a Winbond W83627HF? (Search the board for a chip close to bios chip and the ports)
I've changed the address from 2e to 4e in auto.c and Config.lb, but it didn't change anything.
Ok. This is bad. To some extent. Your southbridge is an ICH4, right? I will go read the ICH4 data sheet some more on thursday to figure something out.
I have a very similar problem with a very similar board, but I did not try 4e yet. Chances are that it's a similar problem.
* Stefan Reinauer stepan@coresystems.de [070604 23:48]:
Ok. This is bad. To some extent. Your southbridge is an ICH4, right? I will go read the ICH4 data sheet some more on thursday to figure something out.
I have a very similar problem with a very similar board, but I did not try 4e yet. Chances are that it's a similar problem.
Do you have a post card?
Hi,
On Mon, Jun 04, Stefan Reinauer wrote:
- Stefan Reinauer stepan@coresystems.de [070604 23:48]:
Ok. This is bad. To some extent. Your southbridge is an ICH4, right? I will go read the ICH4 data sheet some more on thursday to figure something out.
I have a very similar problem with a very similar board, but I did not try 4e yet. Chances are that it's a similar problem.
Do you have a post card?
do you mean a pci or isa card, with two digit display ? A friend of me has an isa card, but my board doesn't have any isa slot. It only has one pci slot (ok two with a riser card).
So I don't have a post card.
Hi Stefan,
On Mon, Jun 04, Stefan Reinauer wrote:
Is your SuperIO a Winbond W83627HF? (Search the board for a chip close to bios chip and the ports)
from the manual it is a winbond W83627HF-AW, but I can't find any chip with those characters on it. I found two chips, which may be a superio controller:
"AL0655 4C229T1 5012D" and "ICS UA 831293 0436 950211BF"
I've changed the address from 2e to 4e in auto.c and Config.lb, but it didn't change anything.
Ok. This is bad. To some extent. Your southbridge is an ICH4, right?
yes:
--snip-- video:~# lspci 00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02) 00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) 00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02) 00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 02) 01:0c.0 Multimedia video controller: Conexant CX23880/1/2/3 PCI Video and Audio Decoder (rev 05) 01:0c.1 Multimedia controller: Conexant CX23880/1/2/3 PCI Video and Audio Decoder [Audio Port] (rev 05) 01:0c.2 Multimedia controller: Conexant CX23880/1/2/3 PCI Video and Audio Decoder [MPEG Port] (rev 05) 01:0c.4 Multimedia controller: Conexant CX23880/1/2/3 PCI Video and Audio Decoder [IR Port] (rev 05) 01:0d.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 02) 01:0f.0 Multimedia controller: Philips Semiconductors SAA7146 (rev 01) --snip--
I will go read the ICH4 data sheet some more on thursday to figure something out.
I have a very similar problem with a very similar board, but I did not try 4e yet. Chances are that it's a similar problem.
hopefully.
Many thanks for your support !
Dieter Bloms wrote:
Hi Stefan,
On Mon, Jun 04, Stefan Reinauer wrote:
Is your SuperIO a Winbond W83627HF? (Search the board for a chip close to bios chip and the ports)
from the manual it is a winbond W83627HF-AW, but I can't find any chip with those characters on it. I found two chips, which may be a superio controller:
"AL0655 4C229T1 5012D" and "ICS UA 831293 0436 950211BF"
Neither of these are it, the first one I think you meant "ALC", which is an audio controller, and the other is a p4 timing chip. Keep looking, here's some popular manufacturers of Super IOs (which would be named on the chip):
Winbond SMSC ITE NSC Fintek
These are just the ones with support in LBv2 and are very common, but there are more out there.
-Corey
Quoting Corey Osgood corey.osgood@gmail.com:
Dieter Bloms wrote:
Hi Stefan,
On Mon, Jun 04, Stefan Reinauer wrote:
Is your SuperIO a Winbond W83627HF? (Search the board for a chip close to bios chip and the ports)
from the manual it is a winbond W83627HF-AW, but I can't find any chip with those characters on it. I found two chips, which may be a superio controller:
"AL0655 4C229T1 5012D" and "ICS UA 831293 0436 950211BF"
Neither of these are it, the first one I think you meant "ALC", which is an audio controller, and the other is a p4 timing chip. Keep looking, here's some popular manufacturers of Super IOs (which would be named on the chip):
Winbond SMSC ITE NSC Fintek
These are just the ones with support in LBv2 and are very common, but there are more out there.
-Corey
Most likely it is eithor a Winbond or SMSC, I have found these are the most popular on Intel P4 boards.
Thanks - Joe
* Dieter Bloms dieter@bloms.de [070605 08:01]:
I will go read the ICH4 data sheet some more on thursday to figure something out.
I have a very similar problem with a very similar board, but I did not try 4e yet. Chances are that it's a similar problem.
hopefully.
Many thanks for your support !
Ok, I have something for a quick try. Can you add the following code to auto.c and try enabling serial once with 2e and once with 4e afterwards?
You might have to adapt the PCI ID of the south bridge's LPC interface device (24cc in the below example)
The code won't patch, but it should serve as a template
Just so we see whether this makes it work.
+++ auto.c (working copy) @@ -69,6 +69,8 @@ }, };
+ unsigned int dev; + if (bist == 0) { early_mtrr_init(); #if 0 @@ -76,7 +78,11 @@ init_timer(); #endif } - + + // enable the decoding of superio ranges to the LPC interface + dev = pci_locate_device(PCI_ID(0x8086, 0x24cc), 0); + pci_write_config16(dev, 0xE6, 0x 3cff); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init();
Hi Stefan,
On Wed, Jun 06, Stefan Reinauer wrote:
Ok, I have something for a quick try. Can you add the following code to auto.c and try enabling serial once with 2e and once with 4e afterwards?
You might have to adapt the PCI ID of the south bridge's LPC interface device (24cc in the below example)
I used 24c0, because of:
00:1f.0 ISA bridge [0601]: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge [8086:24c0] (rev 02)
Just so we see whether this makes it work.
no it doesn't work neither with 2e nor with 4e :(
I think I have something total wrong with my config.
I have tared my stuff, maybe someone is willing to have a look at it:
http://www.bloms.de/download/commell_lv671.tar.gz
* Dieter Bloms dieter@bloms.de [070606 08:36]:
You might have to adapt the PCI ID of the south bridge's LPC interface device (24cc in the below example)
I used 24c0, because of:
00:1f.0 ISA bridge [0601]: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge [8086:24c0] (rev 02)
Ok, that looks correct.
no it doesn't work neither with 2e nor with 4e :(
Pity! Then this is not the only problem at least. I am sure it is required on ICH4 based boards though as ICH4 does not decode any superio at poweron. More at a later time.
I think I have something total wrong with my config.
I have tared my stuff, maybe someone is willing to have a look at it:
On Wed, Jun 06, 2007 at 08:36:31AM +0200, Dieter Bloms wrote:
I have tared my stuff, maybe someone is willing to have a look at it:
Please always post (signed-off) patches, tarballs are hard to review and comment on.
In Config.lb you have
option ROM_SIZE=512*1024+128*1024
which looks wrong. ROM_SIZE is the size of your chip, which is probably 512*1024.
Issue 2:
option USE_FALLBACK_IMAGE=0
should probably be set to 1. If you only use one image it has to be the fallback image AFAIK, otherwise it won't work.
Other than that I cannot spot any obvious problems with the code, it _should_ work, usually...
Uwe.
Hi,
On Wed, Jun 06, Uwe Hermann wrote:
On Wed, Jun 06, 2007 at 08:36:31AM +0200, Dieter Bloms wrote:
I have tared my stuff, maybe someone is willing to have a look at it:
Please always post (signed-off) patches, tarballs are hard to review and comment on.
ok, I will do it in future.
In Config.lb you have
option ROM_SIZE=512*1024+128*1024
which looks wrong. ROM_SIZE is the size of your chip, which is probably 512*1024.
without +128*1024 I got a to liddle rom file, but I will correct this and will see, where to change values to get the right rom sizes. I saw this by another motherboards like tyan/s2850 board
Issue 2:
option USE_FALLBACK_IMAGE=0
should probably be set to 1. If you only use one image it has to be the fallback image AFAIK, otherwise it won't work.
ok, will change that.
Other than that I cannot spot any obvious problems with the code, it _should_ work, usually...
On Thu, Jun 07, 2007 at 08:34:19AM +0200, Dieter Bloms wrote:
which looks wrong. ROM_SIZE is the size of your chip, which is probably 512*1024.
without +128*1024 I got a to liddle rom file, but I will correct this and will see, where to change values to get the right rom sizes.
I think you need something like this:
option ROM_SIZE=512*1024 option FALLBACK_SIZE=ROM_SIZE
Yeah, this sizing stuff is highly confusing and unintuitive. It will all be gone in LinuxBIOSv3 which will be a lot easier to use...
Uwe.
On Mon, Jun 04, 2007 at 11:42:44PM +0200, Dieter Bloms wrote:
/* Setup the console */ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); print_err("Hello\n");
Are you sure your hardware setup is working otherwise? Can you leave the null-modem cable attached as it is right now, but boot a normal Linux system on both ends of the cable? Then run minicom, 115200 BAUD on both sides, and test whether the trasmission itself works?
Do you use real serial ports or some USB-to-serial thingy? I had some problems with these devices in the past, a real serial port might be more reliable...
Uwe.
* Uwe Hermann uwe@hermann-uwe.de [070606 23:57]:
Are you sure your hardware setup is working otherwise? Can you leave the null-modem cable attached as it is right now, but boot a normal Linux system on both ends of the cable? Then run minicom, 115200 BAUD on both sides, and test whether the trasmission itself works?
The south bridge code needs not only the SuperIO ports enabled but also the COM1/COM2 ports. I think Corey's unified ICH code does this.
Hi Uwe,
On Wed, Jun 06, Uwe Hermann wrote:
On Mon, Jun 04, 2007 at 11:42:44PM +0200, Dieter Bloms wrote:
/* Setup the console */ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); print_err("Hello\n");Are you sure your hardware setup is working otherwise? Can you leave the null-modem cable attached as it is right now, but boot a normal Linux system on both ends of the cable? Then run minicom, 115200 BAUD on both sides, and test whether the trasmission itself works?
it works, because my system is connected via wlan and sometimes the driver hangs up. Then I log in via serial cable and reload the driver.
Do you use real serial ports or some USB-to-serial thingy? I had some problems with these devices in the past, a real serial port might be more reliable...
yes there are real serial drivers on both sides.
-
Corey Osgood -
Dieter Bloms -
joe＠smittys.pointclark.net -
Joseph Smith
-
Marc Jones -
Stefan Reinauer -
Uwe Hermann