hi,
so finally, I spent some time on porting coreboot to the asus board "m5a99x evo". http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ I was equipped with three DIP chips and decided to use my target machine also for developing. I had also set up a quite complicated configuration for serial debugging, as I didn't own a second machine with a rs232 board. Although the first try (just flash the "m5a88-v" configuration) showed some output :-) ( http://tinyurl.com/89a33m5 ), the build cycle was a pain in the ass. (0) building coreboot (takes some seconds...) (1) flashing the chip (~30seconds, without verifying) (2) reboot (~20sec) (3) starting coreboot and analyse the output (between 1sec and some minutes ;-)) (4) switch chip with vendor bios on it (some seconds) (5) booting vendor bios and linux (35sec + 11sec. yes, the vendor firmware takes three times longer than linux + x11. BOAR ;-)) (6) switch chip again.
So I was looking for alternatives. I remembered the ft2232 stuff by Uwe. I had it anyway on my "order it some day"-list, so it was the right time ;-) In the meanwhile, I refit my old machine with a new hdd and a reasoneable graphic card. Luckily, it has also a serial port :-) I was a bit afraid of building a programmer (the ft2232 thingy) as I'm not really the hardware guy. However, the first dump was successful. Writing was working too. I was impressed :-) Thanks to Uwe at this point!
So the build cycle is more convenient now: (0) building coreboot (takes longer than on my new machine, but it's okay ;-)) (1) flash the chip with the ft2232 thingy (~30 seconds, without verifying) (2) put the chip onto the mainboard (3) start machine and watch serial output
all in all, it take like one minute to test one build. nice!
So, now I was able to do some serious coreboot hacking. I started from the "m5a88-v" port. What I did: - Changed the southbridge from "SB800" to "SB900" - Adapted some compile-breaks due to this change. - hardcoded some pci device instead of locating it @ early.c -> ohai ramstage :-) - again, some pci related change/hack (aborting the enumeration earlier). I didn't really understand what I did here, I just figured out it hangs here (could be related with the quirk below). After that -> OHAI SEABIOS!
I was very happy ;) However, SeaBIOS itself hang somewhere. In the meanwhile, Kerry pushed RD890 patches, which seemed to be more appropriate for my board (i used RS780 code so far, hence the ugly hacks mentioned above I guess). So I used them, and it felt much cleaner immediately. The payload was still loading -> nice.
After that, I investigated a bit what the problem is with SeaBIOS. At this moment, it hanged after printing "Relocating init from 0x000e8450 to 0xcffd57a0 (size 42812)" (see http://tinyurl.com/78evzex ). I looked into the SeaBIOS code and found out, that you can disable relocation. So I did.
The result was a bit more confusing. http://tinyurl.com/7uh8xty The output get distorted (which seems not to be deterministically, http://tinyurl.com/6opakzl ) and something issues a soft reset (but not everytime...). Eventually I gave up at this point (had to do other stuff anyway). I guess it is something wrong with RAM initialization as relocation in higher memory regions doesn't work. Also, the graphic card isn't found on the pci bus as the RD890 code inlcudes a quirk which "disable all pcie bridges" aka `sr56x0_rd890_disable_pcie_bridge()'. According to `lspci' (with vendor bios), the graphic card is on bus 1, so this seem reasonably. @Kerry: is there some way to enable it again after "early"?
my WIP branch is available here (please tell me if you pull from it, because atm I'm rebasing stuff on it and using `git push -f' to overwrite it...): http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=shortlog;h=refs/heads/W...
full logs (including config and rom images) are available here: http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=tree
Some questions: - What does "CIMX" stands for? I grep'd my #coreboot logs for it. One guy asked that already, but he didn't get an answer :-/ - What's the best/easiest way to verify if RAM init was successful? - I think it would be nice to have an entry on the wiki page for this board. How I get an account? Stefan? :-)
I appreciate any comment, I know resources are short :-( anyways, it was fun and exciting so far :-) thanks!
regards, bernhard
On Wed, Nov 23, 2011 at 10:29 PM, Bernhard Urban lewurm@gmail.com wrote:
Hi Chris,
I reported flashrom compatibility here: http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html
Regarding coreboot support: I'll try to port coreboot to this board. I already have two additional flashchips and at the moment I'm waiting for a serial port connector. I don't know how long it'll talke to port it, but don't except anything useful in less than three months, since I'm new to coreboot (and lazy :-))
Bernhard
On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver zeonglow@googlemail.com wrote:
Hello, I noticed earlier versions of this board are fully supported, but not this one. I have attached the output of, lspci, flashrom and dmidecode, if that is any use to anyone. The spec sheet is easy to find by typing ASUS M5 A99X into Google. The board does have a neat feature of being able to flash the BIOS from within the BIOS menu, which I have already used to update it. Many thanks Chris
-
Bernhard Urban