[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Stefan Reinauer]

Hi,

the attached patch does the following:
- renames LinuxBIOS to coreboot; in addition you need to mv linuxbios.c
coreboot.c and mv linuxbios_tables.h coreboot_tables.h
- fixes cross compilation with an i386-elf- cross toolchain. i.e. drop
all illegal use of system headers, use $(OBJCOPY) instead of objcopy,
add $(CROSS)
- instead of preprocessing bootsect.S into bootsect.s, the intermediate
file is now called bootsect.pre.s. This fixes compilation of memtest86+
on case insensitive filesystems (like NTFS and HFS+)
- Drop unused HWRPB coreboot table type
- Add support for coreboot table forward. The coreboot table may live
somewhere else in memory, in which case there's only a "forwarder" in
the lower 1MB of memory.

Best regards,
Stefan

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Peter Stuge]

Stefan Reinauer wrote:
> +++ memtest86+-4.00/linuxbios.c	2010-01-23 12:45:06.000000000 +0100

..
> @@ -54,16 +54,16 @@
>  }
>
> #define for_each_lbrec(head, rec) \
> for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
> for(rec = (struct cb_record *)(((char *)head) + sizeof(*head)); \

The macro name above still has lb - should that change too?

//Peter

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Stefan Reinauer]

On 1/23/10 4:17 PM, Peter Stuge wrote:
> Stefan Reinauer wrote:
> > +++ memtest86+-4.00/linuxbios.c	2010-01-23 12:45:06.000000000 +0100
>
> ..
> > @@ -54,16 +54,16 @@
> >  }
> >
> > #define for_each_lbrec(head, rec) \
> > for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
> > for(rec = (struct cb_record *)(((char *)head) + sizeof(*head)); \
>
> The macro name above still has lb - should that change too?
>
> //Peter

Yes, absolutely. New patch attached.

Stefan

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Samuel D.]

I don't have any way to test this patch right now, so I'll just add it in
upcoming 4.01.

Thanks for your work.

Sam.

De : Stefan Reinauer [mailto:[e-mail]] 
Envoyé : samedi 23 janvier 2010 16:24
À : coreboot; [e-mail]; Myles Watson
Objet : Re: [coreboot] [PATCH] Update LinuxBIOS/coreboot support in
memtest86+ 4.0

On 1/23/10 4:17 PM, Peter Stuge wrote:

Stefan Reinauer wrote:

+++ memtest86+-4.00/linuxbios.c 2010-01-23 12:45:06.000000000 +0100

..

@@ -54,16 +54,16 @@
 }

#define for_each_lbrec(head, rec) \
- for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
+ for(rec = (struct cb_record *)(((char *)head) + sizeof(*head)); \

The macro name above still has lb - should that change too?

//Peter

Yes, absolutely. New patch attached.

Stefan

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Stefan Reinauer]

On 1/23/10 5:43 PM, Samuel D. wrote:
> I don't have any way to test this patch right now, so I'll just add it
> in upcoming 4.01.
>
> Thanks for your work.
>
> Sam.

Dear Sam,

there was an additional bug I introduced. On top of the other patch, you
need to apply this:
*
Index: coreboot.c
===================================================================
--- coreboot.c    (revision 2775)
+++ coreboot.c    (working copy)
@@ -123,7 +123,8 @@
         /* if there is, all valid information is in the
          * referenced coreboot table
          */
-        head = __find_cb_table(forward->forward, 0x1000);
+        head = __find_cb_table(forward->forward,
+                forward->forward + 0x1000);
     }

return head;
*
In addition I suggest to add the following patch:

*Index: memsize.c
===================================================================
--- memsize.c    (revision 2775)
+++ memsize.c    (working copy)
@@ -125,7 +125,7 @@
         n++;
     }
     v->msegs = n;
-    cprint(LINE_INFO, COL_MMAP, "corebt");
+    cprint(LINE_INFO, COL_MMAP, "coreboot");
 }
 static void memsize_820()
 {*

The other memory table types only output 6 characters here, but the
field is 8 characters, so no need to abbreviate.
Sorry I didn't notice this earlier.

Best regards,
   Stefan

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Knut Kujat]

I tried it with and without the little patch below ( and of course with
the "big" patch) and it freezes after 2 seconds:

Memtest86+ v4.00      | Pass  0%
AMD K10 (65nm) @ 2000 MHz   | Test  3% #
L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
Memory  :   16G   1122 MB/s       
|-------------------------------------------------
Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)

WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
ECC Errs
 ---------  ------  -------  --------  -----  ---  ----  ----  ------
--------
   0:00:02        16G       0K                coreboot      on       
off       Std     0       0
 -----------------------------------------------------------------------------

If you need some more output of whatever just ask me.

bye and thx,
Knut Kujat

Stefan Reinauer escribió:
> On 1/23/10 5:43 PM, Samuel D. wrote:
> > I don't have any way to test this patch right now, so I'll just add
> > it in upcoming 4.01.
> >
> > Thanks for your work.
> >
> > Sam.
>
> Dear Sam,
>
> there was an additional bug I introduced. On top of the other patch,
> you need to apply this:
> Index: coreboot.c
>
> --- coreboot.c    (revision 2775)
> +++ coreboot.c    (working copy)
> @@ -123,7 +123,8 @@
>          /* if there is, all valid information is in the
>           * referenced coreboot table
>           */
>    head = __find_cb_table(forward->forward, 0x1000);
>    head = __find_cb_table(forward->forward,
>            forward->forward + 0x1000);
>
> }
>
> return head;
>
> In addition I suggest to add the following patch:
> *Index: memsize.c
>
> --- memsize.c    (revision 2775)
> +++ memsize.c    (working copy)
> @@ -125,7 +125,7 @@
>          n++;
>      }
>      v->msegs = n;
> cprint(LINE_INFO, COL_MMAP, "corebt");
> cprint(LINE_INFO, COL_MMAP, "coreboot");
>
> }
>  static void memsize_820()
>  {*
>
> The other memory table types only output 6 characters here, but the
> field is 8 characters, so no need to abbreviate.
> Sorry I didn't notice this earlier.
>
> Best regards,
>    Stefan

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Stefan Reinauer]

Knut,

are the values the same as with the vendor bios? Do you get any errors
at all, or does it just hang?

Stefan

On 1/26/10 5:48 PM, Knut Kujat wrote:
> I tried it with and without the little patch below ( and of course with
> the "big" patch) and it freezes after 2 seconds:
>
> Memtest86+ v4.00      | Pass  0%
> AMD K10 (65nm) @ 2000 MHz   | Test  3% #
> L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
> L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
> L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
> Memory  :   16G   1122 MB/s       
> |-------------------------------------------------
> Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
> Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
>
> WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
> ECC Errs
>
> 0:00:02        16G       0K                coreboot      on       
> off       Std     0       0
>
> If you need some more output of whatever just ask me.
>
> bye and thx,
> Knut Kujat

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Knut Kujat]

I haven't tried with a unpatched version of memtest86+ 4.0 and it works
with vendor BIOS. Now with the patched version it halts with coreboot
without error messages (the output you see below is what I see until I
press reset button) and with vendor BIOS its reboots at the same point
(after 2 sec).

bye and thx,
Knut Kujat.

Stefan Reinauer escribió:
> Knut,
>
> are the values the same as with the vendor bios? Do you get any errors
> at all, or does it just hang?
>
> Stefan
>
> On 1/26/10 5:48 PM, Knut Kujat wrote:
> > I tried it with and without the little patch below ( and of course with
> > the "big" patch) and it freezes after 2 seconds:
> >
> > Memtest86+ v4.00      | Pass  0%
> > AMD K10 (65nm) @ 2000 MHz   | Test  3% #
> > L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
> > L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
> > L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
> > Memory  :   16G   1122 MB/s       
> > |-------------------------------------------------
> > Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
> > Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
> >
> > WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
> > ECC Errs
> >
> > 0:00:02        16G       0K                coreboot      on       
> > off       Std     0       0
> >
> > If you need some more output of whatever just ask me.
> >
> > bye and thx,
> > Knut Kujat

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Knut Kujat]

Knut Kujat escribió:
> I haven't tried with a unpatched version of memtest86+ 4.0 and it works

typo!! I meant I HAVE tried memtest86+ 4.0 with a non patched version
and vendor BIOS and it worked.
> with vendor BIOS. Now with the patched version it halts with coreboot
> without error messages (the output you see below is what I see until I
> press reset button) and with vendor BIOS its reboots at the same point
> (after 2 sec).
>
> bye and thx,
> Knut Kujat.
>
> Stefan Reinauer escribió:
> > Knut,
> >
> > are the values the same as with the vendor bios? Do you get any errors
> > at all, or does it just hang?
> >
> > Stefan
> >
> > On 1/26/10 5:48 PM, Knut Kujat wrote:
> > > I tried it with and without the little patch below ( and of course with
> > > the "big" patch) and it freezes after 2 seconds:
> > >
> > > Memtest86+ v4.00      | Pass  0%
> > > AMD K10 (65nm) @ 2000 MHz   | Test  3% #
> > > L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
> > > L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
> > > L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
> > > Memory  :   16G   1122 MB/s       
> > > |-------------------------------------------------
> > > Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
> > > Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
> > >
> > > WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
> > > ECC Errs
> > >
> > > 0:00:02        16G       0K                coreboot      on       
> > > off       Std     0       0
> > >
> > > If you need some more output of whatever just ask me.
> > >
> > > bye and thx,
> > > Knut Kujat

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Stefan Reinauer]

On 1/27/10 10:35 AM, Knut Kujat wrote:
> Knut Kujat escribió:
> > I haven't tried with a unpatched version of memtest86+ 4.0 and it works
>
> typo!! I meant I HAVE tried memtest86+ 4.0 with a non patched version
> and vendor BIOS and it worked.

Are you saying that the patch breaks Vendor BIOS, too?

Stefan
> > with vendor BIOS. Now with the patched version it halts with coreboot
> > without error messages (the output you see below is what I see until I
> > press reset button) and with vendor BIOS its reboots at the same point
> > (after 2 sec).
> >
> > bye and thx,
> > Knut Kujat.
> >
> > Stefan Reinauer escribió:
> > > Knut,
> > >
> > > are the values the same as with the vendor bios? Do you get any errors
> > > at all, or does it just hang?
> > >
> > > Stefan
> > >
> > > On 1/26/10 5:48 PM, Knut Kujat wrote:
> > > > I tried it with and without the little patch below ( and of course with
> > > > the "big" patch) and it freezes after 2 seconds:
> > > >
> > > > Memtest86+ v4.00      | Pass  0%
> > > > AMD K10 (65nm) @ 2000 MHz   | Test  3% #
> > > > L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
> > > > L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
> > > > L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
> > > > Memory  :   16G   1122 MB/s       
> > > > |-------------------------------------------------
> > > > Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
> > > > Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
> > > >
> > > > WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
> > > > ECC Errs
> > > >
> > > > 0:00:02        16G       0K                coreboot      on       
> > > > off       Std     0       0
> > > >
> > > > If you need some more output of whatever just ask me.
> > > >
> > > > bye and thx,
> > > > Knut Kujat

[PATCH] Update LinuxBIOS/coreboot support in memtest86+ 4.0

[Knut Kujat]

Stefan Reinauer escribió:
> On 1/27/10 10:35 AM, Knut Kujat wrote:
> > Knut Kujat escribió:
> > > I haven't tried with a unpatched version of memtest86+ 4.0 and it works
> >
> > typo!! I meant I HAVE tried memtest86+ 4.0 with a non patched version
> > and vendor BIOS and it worked.
>
> Are you saying that the patch breaks Vendor BIOS, too?
>
> Stefan

Unfortunately yes.  With the patched  memtest86+ 4.0  the only
difference between coreboot and vendor bios is that coreboot freezes the
screen completely and vendor bios reboots. And both actions happen at,
as far as I can tell, the same point or time.

thx,
Knut Kujat.
> > > with vendor BIOS. Now with the patched version it halts with coreboot
> > > without error messages (the output you see below is what I see until I
> > > press reset button) and with vendor BIOS its reboots at the same point
> > > (after 2 sec).
> > >
> > > bye and thx,
> > > Knut Kujat.
> > >
> > > Stefan Reinauer escribió:
> > > > Knut,
> > > >
> > > > are the values the same as with the vendor bios? Do you get any errors
> > > > at all, or does it just hang?
> > > >
> > > > Stefan
> > > >
> > > > On 1/26/10 5:48 PM, Knut Kujat wrote:
> > > > > I tried it with and without the little patch below ( and of course with
> > > > > the "big" patch) and it freezes after 2 seconds:
> > > > >
> > > > > Memtest86+ v4.00      | Pass  0%
> > > > > AMD K10 (65nm) @ 2000 MHz   | Test  3% #
> > > > > L1 Cache:   64K  30303 MB/s      | Test #0  [Address test, walking ones]
> > > > > L2 Cache:  512K  10050 MB/s     | Testing: 4096M - 6144M   16G
> > > > > L3 Cache: 2048K   5649 MB/s     | Pattern:   00000000
> > > > > Memory  :   16G   1122 MB/s       
> > > > > |-------------------------------------------------
> > > > > Chipset : AMD K10 IMC (ECC : Detect / Correct - Chipkill : Off)
> > > > > Settings: RAM : 333 MHz (DDR667) / CAS : 5-5-5-15 / DDR2 (64 bits)
> > > > >
> > > > > WallTime   Cached  RsvdMem   MemMap   Cache  ECC  Test  Pass  Errors
> > > > > ECC Errs
> > > > >
> > > > > 0:00:02        16G       0K                coreboot      on       
> > > > > off       Std     0       0
> > > > >
> > > > > If you need some more output of whatever just ask me.
> > > > >
> > > > > bye and thx,
> > > > > Knut Kujat