Dear coreboot folks,
running fwts V16.03.00 [1] on the ASRock E350M1, the following test fails.
``` FAILED [MEDIUM] MSRCPUsInconsistent: Test 1, MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs (shift: 0 mask: 0xffffffffffffffff). MSR CPU 0 -> 0xf77d0ab0 vs CPU 1 -> 0xf77e2ab0 ```
The same problem with different values is reported when running the vendor firmware.
``` FAILED [MEDIUM] MSRCPUsInconsistent: Test 1, MSR 0x00000175 SYSENTER_ESP has 1 inconsistent values across 2 CPUs (shift: 0 mask: 0xffffffffffffffff). MSR CPU 0 -> 0xf79d076c vs CPU 1 -> 0xf79e276c ```
I wonder if it’s an AGESA problem, or if it’s a false positive.
Have you ever seen this?
Thanks,
Paul
[1] https://wiki.ubuntu.com/FirmwareTestSuite Firmware Test Suite (fwts)
Hi all,
This MSR is used when SYSENTER instruction is used by OS/application. The ESP MSR usually points to to the kernel stack of current thread, so if two different threads execute on different CPUs it will be different. False positive, and they should fix it.
Thanks Rudolf
Dear Rudolf,
Am Sonntag, den 15.05.2016, 19:49 +0200 schrieb Rudolf Marek:
This MSR is used when SYSENTER instruction is used by OS/application. The ESP MSR usually points to to the kernel stack of current thread, so if two different threads execute on different CPUs it will be different. False positive, and they should fix it.
Thank you very much for clearing that up.
I submitted a bug report [1], and there is a patch up for review disabling the tests [2].
Could you please confirm that disabling the other two MSR tests for CS and EIP is also the right thing to do?
Thanks,
Paul
[1] https://bugs.launchpad.net/bugs/1582005 [2] https://lists.ubuntu.com/archives/fwts-devel/2016-May/007917.html
Hi all,
Could you please confirm that disabling the other two MSR tests for CS and EIP is also the right thing to do?
Yes I think this is OK. The SYSENTER MSRs are used by the OS and there is nothing which BIOS needs to setup.
Same case is the SYSCALL MSR, GS/FS base and KERNEL GS base and possibly also MSR_TSC_AUX.
#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
Thanks Rudolf