Dear Sir.
This issue was resolved.
Cause is *"size of coreboot.bin"*
My work history is see below.
1. Replace the flash memory on my EVB My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
2. Change value of "ROM chip size" 8 MB to 16 MB
3. run make I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
*But this image is boot fail on my EVB* =>*I don't understand*
4. revert "ROM chip size" I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=> *booting is success*, *But GbE is not running.*
5. replace the flash memory chip 16MByte to 8MByte. I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=> *booting is success*, *GbE is running.*
*Anyway*, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi,
You are using the Intel Rangeley FSP 4.0 release.
I assume that you downloaded this from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su...
With this download you should have received the supporting documentation, including the FSP Integration Guide.
Also included in the download you should have received the RangeleyFsp.bsf file.
This BSF file can be used with the Intel BCT, also available on http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... , to configure settings in the Intel FSP binary.
Review the FSP Integration Guide for more info regarding the FSP binary configuration settings.
Maybe you have configured the Rangeley FSP binary to disable the GbE devices.
Use the BCT to enable the GbE devices, look for the “Enable LAN” option.
Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure.
Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”.
Regards,
David
*From:*coreboot [mailto:coreboot-bounces@coreboot.org] *On Behalf Of *WANG FEI *Sent:* Thursday, June 23, 2016 10:16 PM *To:* 김유석poplinux0@gmail.com *Cc:* coreboot coreboot@coreboot.org *Subject:* Re: [coreboot] The GbE is not activated on my Board.
Can you send me the descriptor.bin and your coreboot image? I can review it.
BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test.
On Wed, Jun 22, 2016 at 7:37 AM, 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com> wrote:
Dear Sir. I have already defined the "CONFIG_IFD_BIN_PATH" *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* And successfully add to coreboot.bin poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But, GbE still not running. Please advise to me. Thank you. 2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work! On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0@gmail.com <mailto:poplinux0@gmail.com>> wrote: Dear Sir. Thank's your prompt reply. My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both. This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT) *- attach the descriptor.bin * I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB. *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* *- Not exist "INCLUDE_ME" and "ME_PATH"* I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree. I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword. *poplinux@raw coreboot $ > ls* 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT Please advise to me. Thank you. 2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei@gmail.com <mailto:wangfei.jimei@gmail.com>> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config? On Mon, Jun 20, 2016 at 6:46 AM, 김유석 <poplinux0@gmail.com <mailto:poplinux0@gmail.com>> wrote: Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI). *This image is actvate the GbE*. Another developer was same quetion to Coreboot communite. And He is resolved this issue. https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html This guy's said that "Must add the descriptor.bin to coreboot.bin". So, I was extract the descriptor.bin from ADI's coreboot.bin And successfully attached the descriptor.bin to my coreboot.bin. *oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.* *poplinux@raw bins $ >* ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) *poplinux@raw bins $ >* ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin *poplinux@raw bins $ >* ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But GbE is still de-activated. boot log is see below. PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled *PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it*. I don't have a any idea for activate the GbE. Please advise to me. Thank you. -- coreboot mailing list: coreboot@coreboot.org <mailto:coreboot@coreboot.org> https://www.coreboot.org/mailman/listinfo/coreboot
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Hi,
The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash.
As only 4GB can be mapped into memory that the CPU can read, it's pointless to use 16GB flash or more, unless you need more space for TXE (Trusted Execution Engine) applications. Only the TXE Sparc processor can read the wasted memory.
You can read all the memory using SPI controller read cycles, but that is not generally a good idea.
Best regards,
B-O Bergman Winzent Technologies
29 juni 2016 kl. 09:14 skrev 김유석 poplinux0@gmail.com:
Dear Sir.
This issue was resolved.
Cause is "size of coreboot.bin"
My work history is see below.
- Replace the flash memory on my EVB
My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
- Change value of "ROM chip size" 8 MB to 16 MB
<hcglehbmiikmmgbd.png>
- run make
I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
But this image is boot fail on my EVB => I don't understand
- revert "ROM chip size"
I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=> booting is success, But GbE is not running.
- replace the flash memory chip 16MByte to 8MByte.
I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=> booting is success, GbE is running.
Anyway, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi,
You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available on http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html , to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings.
Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option.
Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”.
Regards, David <> <>From: coreboot [mailto:coreboot-bounces@coreboot.org mailto:coreboot-bounces@coreboot.org] On Behalf Of WANG FEI Sent: Thursday, June 23, 2016 10:16 PM To: 김유석 poplinux0@gmail.com mailto:poplinux0@gmail.com Cc: coreboot coreboot@coreboot.org mailto:coreboot@coreboot.org Subject: Re: [coreboot] The GbE is not activated on my Board.
Can you send me the descriptor.bin and your coreboot image? I can review it.
BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test.
On Wed, Jun 22, 2016 at 7:37 AM, 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
I have already defined the "CONFIG_IFD_BIN_PATH"
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
And successfully add to coreboot.bin
poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But, GbE still not running.
Please advise to me.
Thank you.
2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work!
On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
Thank's your prompt reply.
My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both.
This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT)
attach the descriptor.bin
I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB.
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
<Brevbilaga.jpeg>
Not exist "INCLUDE_ME" and "ME_PATH"
I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree.
I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword.
poplinux@raw coreboot $ > ls 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util
poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn
poplinux@raw coreboot $ > grep "ME_PATH" * -Rn cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT
Please advise to me.
Thank you.
2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: Here is a sample,
Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample).
On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei@gmail.com mailto:wangfei.jimei@gmail.com> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config?
On Mon, Jun 20, 2016 at 6:46 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
My ENV
EVB : ADI SG-2440
source : official coreboot
FSP : intel FSP 4.0
I was successfully build-up the coreboot and successfully boot-up my EVB.
But My EVB's GbE is not activated(not running.)
So, I was try to boot using the original OEM bios(from ADI). This image is actvate the GbE.
Another developer was same quetion to Coreboot communite. And He is resolved this issue.
https://www.coreboot.org/pipermail/coreboot/2015-January/079074.htmlhttps://www.coreboot.org/pipermail/coreboot/2015-January/079074.html https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html
This guy's said that "Must add the descriptor.bin to coreboot.bin".
So, I was extract the descriptor.bin from ADI's coreboot.bin
And successfully attached the descriptor.bin to my coreboot.bin.
oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.
poplinux@raw bins $ > ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
poplinux@raw bins $ > ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin poplinux@raw bins $ > ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But GbE is still de-activated. boot log is see below.
PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it.
I don't have a any idea for activate the GbE.
Please advise to me.
Thank you.
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Dear Sir.
Thank's your answer.
I have a some more question for you. * **1. Must create the coreboot.bin under 4MB?* You mean, "_You must create the coreboot.bin under 4MB size?_" Is it correct?
If i create the 8MByte size, It will be _unstable_? or _stable_?
*2. 4GB or 4MB?* You said to me that "The BIOS image is limited to 4GB by hardware" Is it correct or you miss-typing?
*3. Why support 16MByte image the Kconfig of coreboot?* I don't understand that why support 16MByte imge the Kconfig of coreboot. Is it _just misstake_? or have a _any reason_?
Best regards,
Kay.kim.
2016-06-29 오후 5:57에 Berth-Olof Bergman 이(가) 쓴 글:
Hi,
The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash.
As only 4GB can be mapped into memory that the CPU can read, it's pointless to use 16GB flash or more, unless you need more space for TXE (Trusted Execution Engine) applications. Only the TXE Sparc processor can read the wasted memory.
You can read all the memory using SPI controller read cycles, but that is not generally a good idea.
Best regards,
B-O Bergman Winzent Technologies
29 juni 2016 kl. 09:14 skrev 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com>:
Dear Sir.
This issue was resolved.
Cause is*"size of coreboot.bin"*
My work history is see below.
- Replace the flash memory on my EVB
My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
- Change value of "ROM chip size" 8 MB to 16 MB
<hcglehbmiikmmgbd.png>
- run make
I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
*But this image is boot fail on my EVB*=>*I don't understand*
- revert "ROM chip size"
I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=>*booting is success*,*But GbE is not running.*
- replace the flash memory chip 16MByte to 8MByte.
I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=>*booting is success*,*GbE is running.*
*Anyway*, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi, You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this fromhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available onhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su..., to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings. Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option. Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”. Regards, David *From:*coreboot [mailto:coreboot-bounces@coreboot.org]*On Behalf Of*WANG FEI *Sent:*Thursday, June 23, 2016 10:16 PM *To:*김유석poplinux0@gmail.com *Cc:*corebootcoreboot@coreboot.org *Subject:*Re: [coreboot] The GbE is not activated on my Board. Can you send me the descriptor.bin and your coreboot image? I can review it. BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test. On Wed, Jun 22, 2016 at 7:37 AM,김유석<poplinux0@gmail.com mailto:poplinux0@gmail.com> wrote:
Dear Sir. I have already defined the "CONFIG_IFD_BIN_PATH" *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* And successfully add to coreboot.bin poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But, GbE still not running. Please advise to me. Thank you. 2016-06-22오전12:54에WANG FEI이(가)쓴글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work! On Tue, Jun 21, 2016 at 2:16 AM,김유석<poplinux0@gmail.com <mailto:poplinux0@gmail.com>> wrote: Dear Sir. Thank's your prompt reply. My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both. This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT) *- attach the descriptor.bin * I was select the"CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the"CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB. *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* <Brevbilaga.jpeg> *- Not exist "INCLUDE_ME" and "ME_PATH"* I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree. I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword. *poplinux@raw coreboot $ > ls* 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT Please advise to me. Thank you. 2016-06-21오전6:58에WANG FEI이(가)쓴글: Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei@gmail.com <mailto:wangfei.jimei@gmail.com>> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config? On Mon, Jun 20, 2016 at 6:46 AM,김유석<poplinux0@gmail.com> wrote: Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI).*This image is actvate the GbE*. Another developer was same quetion to Coreboot communite. And He is resolved this issue. https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html This guy's said that "Must add the descriptor.bin to coreboot.bin". So, I was extract the descriptor.bin from ADI's coreboot.bin And successfully attached the descriptor.bin to my coreboot.bin. *oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.* *poplinux@raw bins $ >*./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) *poplinux@raw bins $ >*ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin *poplinux@raw bins $ >*./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But GbE is still de-activated. boot log is see below. PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled *PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it*. I don't have a any idea for activate the GbE. Please advise to me. Thank you. -- coreboot mailing list:coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
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Answers to your question follows below.
Best regards,
B-O
30 juni 2016 kl. 03:08 skrev 김유석 poplinux0@gmail.com:
Dear Sir.
Thank's your answer.
I have a some more question for you.
- Must create the coreboot.bin under 4MB?
You mean, "You must create the coreboot.bin under 4MB size?" Is it correct?
If i create the 8MByte size, It will be unstable? or stable?
The chipset is limited to map only 4GB for BIOS firmware.
- 4GB or 4MB?
You said to me that "The BIOS image is limited to 4GB by hardware" Is it correct or you miss-typing?
This is correct.
- Why support 16MByte image the Kconfig of coreboot?
I don't understand that why support 16MByte imge the Kconfig of coreboot. Is it just misstake? or have a any reason?
More than 4MB may be supported on other architectures.
Best regards,
Kay.kim.
2016-06-29 오후 5:57에 Berth-Olof Bergman 이(가) 쓴 글:
Hi,
The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash.
As only 4GB can be mapped into memory that the CPU can read, it's pointless to use 16GB flash or more, unless you need more space for TXE (Trusted Execution Engine) applications. Only the TXE Sparc processor can read the wasted memory.
You can read all the memory using SPI controller read cycles, but that is not generally a good idea.
Best regards,
B-O Bergman Winzent Technologies
29 juni 2016 kl. 09:14 skrev 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com>:
Dear Sir.
This issue was resolved.
Cause is "size of coreboot.bin"
My work history is see below.
- Replace the flash memory on my EVB
My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
- Change value of "ROM chip size" 8 MB to 16 MB
<hcglehbmiikmmgbd.png>
- run make
I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
But this image is boot fail on my EVB => I don't understand
- revert "ROM chip size"
I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=> booting is success, But GbE is not running.
- replace the flash memory chip 16MByte to 8MByte.
I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=> booting is success, GbE is running.
Anyway, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi,
You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.htmlhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available on http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.htmlhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html , to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings.
Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option.
Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”.
Regards, David <> <>From: coreboot [ mailto:coreboot-bounces@coreboot.orgmailto:coreboot-bounces@coreboot.org mailto:coreboot-bounces@coreboot.org] On Behalf Of WANG FEI Sent: Thursday, June 23, 2016 10:16 PM To: 김유석 mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com Cc: coreboot mailto:coreboot@coreboot.orgcoreboot@coreboot.org mailto:coreboot@coreboot.org Subject: Re: [coreboot] The GbE is not activated on my Board.
Can you send me the descriptor.bin and your coreboot image? I can review it.
BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test.
On Wed, Jun 22, 2016 at 7:37 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
I have already defined the "CONFIG_IFD_BIN_PATH"
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
And successfully add to coreboot.bin
poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But, GbE still not running.
Please advise to me.
Thank you.
2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work!
On Tue, Jun 21, 2016 at 2:16 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
Thank's your prompt reply.
My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both.
This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT)
attach the descriptor.bin
I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB.
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
<Brevbilaga.jpeg>
Not exist "INCLUDE_ME" and "ME_PATH"
I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree.
I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword.
poplinux@raw coreboot $ > ls 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util
poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn
poplinux@raw coreboot $ > grep "ME_PATH" * -Rn cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT
Please advise to me.
Thank you.
2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: Here is a sample,
Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample).
On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI < mailto:wangfei.jimei@gmail.comwangfei.jimei@gmail.com mailto:wangfei.jimei@gmail.com> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config?
On Mon, Jun 20, 2016 at 6:46 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
My ENV
EVB : ADI SG-2440
source : official coreboot
FSP : intel FSP 4.0
I was successfully build-up the coreboot and successfully boot-up my EVB.
But My EVB's GbE is not activated(not running.)
So, I was try to boot using the original OEM bios(from ADI). This image is actvate the GbE.
Another developer was same quetion to Coreboot communite. And He is resolved this issue.
https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html
This guy's said that "Must add the descriptor.bin to coreboot.bin".
So, I was extract the descriptor.bin from ADI's coreboot.bin
And successfully attached the descriptor.bin to my coreboot.bin.
oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.
poplinux@raw bins $ > ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
poplinux@raw bins $ > ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin poplinux@raw bins $ > ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But GbE is still de-activated. boot log is see below.
PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it.
I don't have a any idea for activate the GbE.
Please advise to me.
Thank you.
-- coreboot mailing list: coreboot@coreboot.org mailto:coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboothttps://www.coreboot.org/mailman/listinfo/coreboot https://www.coreboot.org/mailman/listinfo/coreboot
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Dear Sir.
Thank's your prompt reply.
Your answer is very nice to me.
Best regards,
Kay.kim
2016-06-30 오후 1:35에 Berth-Olof Bergman 이(가) 쓴 글:
Answers to your question follows below.
Best regards,
B-O
30 juni 2016 kl. 03:08 skrev 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com>:
Dear Sir.
Thank's your answer.
I have a some more question for you.
**1. Must create the coreboot.bin under 4MB?* You mean, "_You must create the coreboot.bin under 4MB size?_" Is it correct?
If i create the 8MByte size, It will be _unstable_? or _stable_?
The chipset is limited to map only 4GB for BIOS firmware.
*2. 4GB or 4MB?* You said to me that "The BIOS image is limited to 4GB by hardware" Is it correct or you miss-typing?
This is correct.
*3. Why support 16MByte image the Kconfig of coreboot?* I don't understand that why support 16MByte imge the Kconfig of coreboot. Is it _just misstake_? or have a _any reason_?
More than 4MB may be supported on other architectures.
Best regards,
Kay.kim.
2016-06-29 오후 5:57에 Berth-Olof Bergman 이(가) 쓴 글:
Hi,
The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash.
As only 4GB can be mapped into memory that the CPU can read, it's pointless to use 16GB flash or more, unless you need more space for TXE (Trusted Execution Engine) applications. Only the TXE Sparc processor can read the wasted memory.
You can read all the memory using SPI controller read cycles, but that is not generally a good idea.
Best regards,
B-O Bergman Winzent Technologies
29 juni 2016 kl. 09:14 skrev 김유석 poplinux0@gmail.com:
Dear Sir.
This issue was resolved.
Cause is*"size of coreboot.bin"*
My work history is see below.
- Replace the flash memory on my EVB
My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
- Change value of "ROM chip size" 8 MB to 16 MB
<hcglehbmiikmmgbd.png>
- run make
I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
*But this image is boot fail on my EVB*=>*I don't understand*
- revert "ROM chip size"
I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=>*booting is success*,*But GbE is not running.*
- replace the flash memory chip 16MByte to 8MByte.
I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=>*booting is success*,*GbE is running.*
*Anyway*, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi, You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this fromhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available onhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su..., to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings. Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option. Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”. Regards, David *From:*coreboot [mailto:coreboot-bounces@coreboot.org]*On Behalf Of*WANG FEI *Sent:*Thursday, June 23, 2016 10:16 PM *To:*김유석poplinux0@gmail.com *Cc:*corebootcoreboot@coreboot.org *Subject:*Re: [coreboot] The GbE is not activated on my Board. Can you send me the descriptor.bin and your coreboot image? I can review it. BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test. On Wed, Jun 22, 2016 at 7:37 AM,김유석poplinux0@gmail.com wrote:
Dear Sir. I have already defined the "CONFIG_IFD_BIN_PATH" *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set * 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* And successfully add to coreboot.bin poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But, GbE still not running. Please advise to me. Thank you. 2016-06-22오전12:54에WANG FEI이(가)쓴글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work! On Tue, Jun 21, 2016 at 2:16 AM,김유석<poplinux0@gmail.com> wrote: Dear Sir. Thank's your prompt reply. My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both. This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT) *- attach the descriptor.bin * I was select the"CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the"CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB. *131 CONFIG_HAVE_IFD_BIN=y* 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set *317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"* <Brevbilaga.jpeg> *- Not exist "INCLUDE_ME" and "ME_PATH"* I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree. I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword. *poplinux@raw coreboot $ > ls* 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util *poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn* *poplinux@raw coreboot $ > grep "ME_PATH" * -Rn* cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT Please advise to me. Thank you. 2016-06-21오전6:58에WANG FEI이(가)쓴글: Here is a sample, Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample). On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI <wangfei.jimei@gmail.com> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config? On Mon, Jun 20, 2016 at 6:46 AM,김유석<poplinux0@gmail.com> wrote: Dear Sir. My ENV EVB : ADI SG-2440 source : official coreboot FSP : intel FSP 4.0 I was successfully build-up the coreboot and successfully boot-up my EVB. But My EVB's GbE is not activated(not running.) So, I was try to boot using the original OEM bios(from ADI).*This image is actvate the GbE*. Another developer was same quetion to Coreboot communite. And He is resolved this issue. https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html This guy's said that "Must add the descriptor.bin to coreboot.bin". So, I was extract the descriptor.bin from ADI's coreboot.bin And successfully attached the descriptor.bin to my coreboot.bin. *oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.* *poplinux@raw bins $ >*./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) *poplinux@raw bins $ >*ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin *poplinux@raw bins $ >*./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00 ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused) Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000 Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000 FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118 FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff But GbE is still de-activated. boot log is see below. PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled *PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it*. I don't have a any idea for activate the GbE. Please advise to me. Thank you. -- coreboot mailing list:coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
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This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
-- coreboot mailing list:coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
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Thank you!
30 juni 2016 kl. 06:38 skrev 김유석 poplinux0@gmail.com:
Dear Sir.
Thank's your prompt reply.
Your answer is very nice to me.
Best regards,
Kay.kim
2016-06-30 오후 1:35에 Berth-Olof Bergman 이(가) 쓴 글:
Answers to your question follows below.
Best regards,
B-O
30 juni 2016 kl. 03:08 skrev 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com>:
Dear Sir.
Thank's your answer.
I have a some more question for you.
- Must create the coreboot.bin under 4MB?
You mean, "You must create the coreboot.bin under 4MB size?" Is it correct?
If i create the 8MByte size, It will be unstable? or stable?
The chipset is limited to map only 4GB for BIOS firmware.
- 4GB or 4MB?
You said to me that "The BIOS image is limited to 4GB by hardware" Is it correct or you miss-typing?
This is correct.
- Why support 16MByte image the Kconfig of coreboot?
I don't understand that why support 16MByte imge the Kconfig of coreboot. Is it just misstake? or have a any reason?
More than 4MB may be supported on other architectures.
Best regards,
Kay.kim.
2016-06-29 오후 5:57에 Berth-Olof Bergman 이(가) 쓴 글:
Hi,
The BIOS image is limited to 4GB by hardware. So the BIOS need to fit within the top 4GB of the flash. Otherwise it will not work. You can concatenate your 8GB images to one 16 GB image and it will work. Thus your BIOS part will be in top of first 8GB and last 8GB of the 16 MB flash.
As only 4GB can be mapped into memory that the CPU can read, it's pointless to use 16GB flash or more, unless you need more space for TXE (Trusted Execution Engine) applications. Only the TXE Sparc processor can read the wasted memory.
You can read all the memory using SPI controller read cycles, but that is not generally a good idea.
Best regards,
B-O Bergman Winzent Technologies
29 juni 2016 kl. 09:14 skrev 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com>:
Dear Sir.
This issue was resolved.
Cause is "size of coreboot.bin"
My work history is see below.
- Replace the flash memory on my EVB
My SG-2440 is have a 8MByte flash memory, But I'll use the 16MByte flash. So, I was replace the flash memory 8MByte to 16MByte.
original flash : WINBOND W25Q64 (8MByte) new flash : WINBOND W25Q128(16MByte)
- Change value of "ROM chip size" 8 MB to 16 MB
<hcglehbmiikmmgbd.png>
- run make
I was successfully build the coreboot. and got a "coreboot.bin". It is 16MByte size.
But this image is boot fail on my EVB => I don't understand
- revert "ROM chip size"
I was revert value of "ROM chip size" to 8MByte. And write to start address 0x800000 on 16MByte flash memory.
=> booting is success, But GbE is not running.
- replace the flash memory chip 16MByte to 8MByte.
I'm try to replace the flash memoy 16MByte to 8MByte. And write to start address 0x00 on 8MByte flash memory.
=> booting is success, GbE is running.
Anyway, I was success "enable the GbE".
But I don't understand this sistuation.
Have a any idea?
Thank you.
2016-06-25 오후 11:46에 Guckian, David 이(가) 쓴 글:
Hi,
You are using the Intel Rangeley FSP 4.0 release. I assume that you downloaded this from http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.htmlhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html With this download you should have received the supporting documentation, including the FSP Integration Guide. Also included in the download you should have received the RangeleyFsp.bsf file. This BSF file can be used with the Intel BCT, also available on http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.htmlhttp://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-su... http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html , to configure settings in the Intel FSP binary. Review the FSP Integration Guide for more info regarding the FSP binary configuration settings.
Maybe you have configured the Rangeley FSP binary to disable the GbE devices. Use the BCT to enable the GbE devices, look for the “Enable LAN” option.
Also, coreboot has the ability to overwrite these settings via the UPD_DATA_REGION structure. Please search your coreboot for PcdEnableLan, if found make sure this is set to “1”.
Regards, David <> <>From: coreboot [mailto:coreboot-bounces@coreboot.org mailto:coreboot-bounces@coreboot.org] On Behalf Of WANG FEI Sent: Thursday, June 23, 2016 10:16 PM To: 김유석 mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com Cc: coreboot mailto:coreboot@coreboot.orgcoreboot@coreboot.org mailto:coreboot@coreboot.org Subject: Re: [coreboot] The GbE is not activated on my Board.
Can you send me the descriptor.bin and your coreboot image? I can review it.
BTW, your image is running on Mohon Peak platform, right? I just have one Mohon Peak platform to test.
On Wed, Jun 22, 2016 at 7:37 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
I have already defined the "CONFIG_IFD_BIN_PATH"
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
And successfully add to coreboot.bin
poplinux@raw coreboot $ > ./ifdtool -d coreboot.bin File src/oem_dumped.bin is 8388608 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But, GbE still not running.
Please advise to me.
Thank you.
2016-06-22 오전 12:54에 WANG FEI 이(가) 쓴 글: INCLUDE_ME & ME_PATH was used before, but it has changed to IFD_BIN_PATH recently. Did you define IFD_BIN_PATH with path/descriptor.bin? It should work!
On Tue, Jun 21, 2016 at 2:16 AM, 김유석 <poplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
Thank's your prompt reply.
My coreboot source code download from coreboot GIT and ADI's coreboot GIT. both.
This time, I work on official coreboot GIT(not ADI's GIT, but i can do ADI's GIT)
attach the descriptor.bin
I was select the "CONFIG_HAVE_IFD_BIN", "CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY", and fill-up the "CONFIG_IFD_BIN_PATH". And descriptor.bin is extract from ADI's EVB.
131 CONFIG_HAVE_IFD_BIN=y 308 # 309 # Southbridge 310 # 311 # CONFIG_AMD_SB_CIMX is not set 312 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set 313 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set 314 CONFIG_SOUTH_BRIDGE_OPTIONS=y 315 # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set 316 # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set 317 CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY=y 318 CONFIG_IFD_BIN_PATH="../bins/descriptor.bin"
<Brevbilaga.jpeg>
Not exist "INCLUDE_ME" and "ME_PATH"
I'm can't setup the "INCLUDE_ME" and "ME_PATH" Because thie keyword is not exist coreboot's source tree.
I was try to find the "INCLUDE_ME" and "ME_PATH" from coreboot source, But not exist this keyword.
poplinux@raw coreboot $ > ls 3rdparty Documentation Makefile README cscope.out src toolchain.inc COPYING MAINTAINERS Makefile.inc build payloads tags util
poplinux@raw coreboot $ > grep "INCLUDE_ME" * -Rn
poplinux@raw coreboot $ > grep "ME_PATH" * -Rn cscope.out:9055111:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16228575:CONFIG_RESUME_PATH_SAME_AS_BOOT cscope.out:16229157:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:354905:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528183:CONFIG_RESUME_PATH_SAME_AS_BOOT src/cscope.out:7528765:CONFIG_RESUME_PATH_SAME_AS_BOOT src/vendorcode/google/chromeos/vboot2/vboot_logic.c:125: if (!IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT)) src/vendorcode/google/chromeos/vboot2/vboot_logic.c:311: if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/drivers/intel/fsp1_1/romstage.c:181: !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && src/Kconfig:540:config RESUME_PATH_SAME_AS_BOOT
Please advise to me.
Thank you.
2016-06-21 오전 6:58에 WANG FEI 이(가) 쓴 글: Here is a sample,
Please select INCLUDE_ME to y and set ME_PATH to point to your descriptor.bin (Path/descriptor.bin, refer to FSP_FILE as a sample).
On Mon, Jun 20, 2016 at 10:48 PM, WANG FEI < mailto:wangfei.jimei@gmail.comwangfei.jimei@gmail.com mailto:wangfei.jimei@gmail.com> wrote: YuSeok, how did you attach the descriptor.bin to your coreboot? Did you follow the previous mail to include descriptor.bin with INCLUDE_ME and ME_PATH in .config?
On Mon, Jun 20, 2016 at 6:46 AM, 김유석 < mailto:poplinux0@gmail.compoplinux0@gmail.com mailto:poplinux0@gmail.com> wrote: Dear Sir.
My ENV
EVB : ADI SG-2440
source : official coreboot
FSP : intel FSP 4.0
I was successfully build-up the coreboot and successfully boot-up my EVB.
But My EVB's GbE is not activated(not running.)
So, I was try to boot using the original OEM bios(from ADI). This image is actvate the GbE.
Another developer was same quetion to Coreboot communite. And He is resolved this issue.
https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html https://www.coreboot.org/pipermail/coreboot/2015-January/079074.html
This guy's said that "Must add the descriptor.bin to coreboot.bin".
So, I was extract the descriptor.bin from ADI's coreboot.bin
And successfully attached the descriptor.bin to my coreboot.bin.
oem_dumped.bin => ADI's default coreboot.bin, This image are activated the GbE.
poplinux@raw bins $ > ./ifdtool -x src/oem_dumped.bin File src/oem_dumped.bin is 8388608 bytes Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff Flash Region 1 (BIOS): 00010000 - 007fffff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) Flash Region 3 (GbE): 00fff000 - 00000fff (unused) Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
poplinux@raw bins $ > ln -s ./flashregion_0_flashdescriptor.bin descriptor.bin poplinux@raw bins $ > ./ifdtool -d ./descriptor.bin File ./descriptor.bin is 65536 bytes FLMAP0: 0x01040003 NR: 1 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x09100206 ISL: 0x09 FPSBA: 0x100 NM: 2 FMBA: 0x60 FLMAP2: 0x00210020 PSL: 0x2100 FMSBA: 0x200 FLUMAP1: 0x000002e0 Intel ME VSCC Table Length (VTL): 2 Intel ME VSCC Table Base Address (VTBA): 0x000e00
ME VSCC table: JID0: 0x001740ef SPI Componend Device ID 1: 0x17 SPI Componend Device ID 0: 0x40 SPI Componend Vendor ID: 0xef VSCC0: 0x20052005 Lower Erase Opcode: 0x20 Lower Write Enable on Write Status: 0x50 Lower Write Status Required: No Lower Write Granularity: 64 bytes Lower Block / Sector Erase Size: 4KB Upper Erase Opcode: 0x20 Upper Write Enable on Write Status: 0x50 Upper Write Status Required: No Upper Write Granularity: 64 bytes Upper Block / Sector Erase Size: 4KB
OEM Section: 00: 31 31 35 32 31 35 30 39 32 30 00 00 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Found Region Section FLREG0: 0x000f0000 Flash Region 0 (Flash Descriptor): 00000000 - 0000ffff FLREG1: 0x07ff0010 Flash Region 1 (BIOS): 00010000 - 007fffff FLREG2: 0x00000fff Flash Region 2 (Intel ME): 00fff000 - 00000fff (unused) FLREG3: 0x00000fff Flash Region 3 (GbE): 00fff000 - 00000fff (unused) FLREG4: 0x00000fff Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)
Found Component Section FLCOMP 0x09200024 Dual Output Fast Read Support: not supported Read ID/Read Status Clock Frequency: 33MHz Write/Erase Clock Frequency: 33MHz Fast Read Clock Frequency: 33MHz Fast Read Support: not supported Read Clock Frequency: 20MHz Component 2 Density: 8MB Component 1 Density: 8MB FLILL 0x00000000 Invalid Instruction 3: 0x00 Invalid Instruction 2: 0x00 Invalid Instruction 1: 0x00 Invalid Instruction 0: 0x00 FLPB 0x00000000 Flash Partition Boundary Address: 0x000000
Found PCH Strap Section PCHSTRP0: 0x00080002 PCHSTRP1: 0x00000000 PCHSTRP2: 0x00000000 PCHSTRP3: 0x00000003 PCHSTRP4: 0x0000007f PCHSTRP5: 0x007fffc0 PCHSTRP6: 0x0001c7c0 PCHSTRP7: 0x00000624 PCHSTRP8: 0x00000000 PCHSTRP9: 0xffffffff PCHSTRP10: 0xffffffff PCHSTRP11: 0xffffffff PCHSTRP12: 0xffffffff PCHSTRP13: 0xffffffff PCHSTRP14: 0xffffffff PCHSTRP15: 0xffffffff PCHSTRP16: 0xffffffff PCHSTRP17: 0xffffffff
Found Master Section FLMSTR1: 0x1f1f0000 (Host CPU/BIOS) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0x0000
FLMSTR2: 0x08090118 (Intel ME) Platform Data Region Write Access: disabled GbE Region Write Access: enabled Intel ME Region Write Access: disabled Host CPU/BIOS Region Write Access: disabled Flash Descriptor Write Access: disabled Platform Data Region Read Access: disabled GbE Region Read Access: enabled Intel ME Region Read Access: disabled Host CPU/BIOS Region Read Access: disabled Flash Descriptor Read Access: enabled Requester ID: 0x0118
FLMSTR3: 0xffffffff (GbE) Platform Data Region Write Access: enabled GbE Region Write Access: enabled Intel ME Region Write Access: enabled Host CPU/BIOS Region Write Access: enabled Flash Descriptor Write Access: enabled Platform Data Region Read Access: enabled GbE Region Read Access: enabled Intel ME Region Read Access: enabled Host CPU/BIOS Region Read Access: enabled Flash Descriptor Read Access: enabled Requester ID: 0xffff
Found Processor Strap Section ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff ????: 0xffffffff
But GbE is still de-activated. boot log is see below.
PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/1f0e] enabled Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/1f10] enabled PCI: Static device PCI: 00:02.0 not found, disabling it. Capability: type 0x10 @ 0x40 Capability: type 0x01 @ 0x80 Capability: type 0x0d @ 0x88 Capability: type 0x05 @ 0x90 Capability: type 0x10 @ 0x40 PCI: 00:03.0 subordinate bus PCI Express PCI: 00:03.0 [8086/1f12] enabled PCI: Static device PCI: 00:04.0 not found, disabling it. PCI: 00:0b.0 [8086/1f18] enabled PCI: 00:0e.0 [8086/1f14] enabled PCI: 00:0f.0 [8086/1f16] enabled PCI: 00:13.0 [8086/1f15] enabled PCI: Static device PCI: 00:14.0 not found, disabling it. PCI: Static device PCI: 00:14.1 not found, disabling it. PCI: Static device PCI: 00:14.2 not found, disabling it. PCI: Static device PCI: 00:14.3 not found, disabling it.
I don't have a any idea for activate the GbE.
Please advise to me.
Thank you.
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