Hi all, Does Coreboot write to the flash chip it resides on? Can this be disabled? Verify of the SPI bios chip fails once the unit has booted up at least once.
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Hi Naveed,
It's probably the MRC cache or something like that, which IIRC you can disable. Whether there is also something else writing to the chip from coreboot I'm not 100% but others will chime in on that, I'm sure.
Kind Regards,
John.
On 27/02/17 08:15, Naveed Ghori wrote:
Hi all,
Does Coreboot write to the flash chip it resides on? Can this be disabled?
Verify of the SPI bios chip fails once the unit has booted up at least once.
Best Regards,
Naveed
*Naveed Ghori* | Lead Firmware & Driver Engineer *DTI Group Ltd* | Transit Security & Surveillance
31 Affleck Road, Perth Airport, Western Australia 6105, Australia P +61 8 9373 2905,151 | F +61 8 9479 1190 | naveed.ghori@dti.com.au mailto:naveed.ghori@dti.com.au
Visit our website www.dti.com.au http://www.dti.com.au The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.
It's probably the MRC cache...
Agreed, if this feature is enabled it will reliably modify the flash contents during the first boot. This can typically be disabled under the chipset menu. You may need to look for something like "Enable Fast Boot" but I suspect this text could be inconsistent across technologies.
The Intel ME can also modify the contents without your knowledge, e.g. for logging. This could potentially be more intermittent, though. For good measure, you probably want to use the Intel FITC tool and ensure ME logging is disabled on your system. (This is NDA only, I believe.)
Since you didn't mention your CPU vendor, the AMD PSP can also modify the flash device contents in its firmware area.
Of course, if you can read the device and identify the address of the change, that will give you clues for determining how it's getting modified.
Thanks, Marshall
On Mon, Feb 27, 2017 at 2:38 AM, John Lewis jlewis@johnlewis.ie wrote:
Hi Naveed,
It's probably the MRC cache or something like that, which IIRC you can disable. Whether there is also something else writing to the chip from coreboot I'm not 100% but others will chime in on that, I'm sure.
Kind Regards,
John.
On 27/02/17 08:15, Naveed Ghori wrote:
Hi all,
Does Coreboot write to the flash chip it resides on? Can this be disabled?
Verify of the SPI bios chip fails once the unit has booted up at least once.
Best Regards,
Naveed *Naveed Ghori* | Lead Firmware & Driver Engineer *DTI Group Ltd* | Transit Security & Surveillance 31 Affleck Road, Perth Airport, Western Australia 6105, Australia P +61 8 9373 2905,151 | F +61 8 9479 1190 <+61%208%209479%201190> | naveed.ghori@dti.com.au Visit our website www.dti.com.au The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.
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* John Lewis jlewis@johnlewis.ie [170227 10:38]:
Hi Naveed,
It's probably the MRC cache or something like that, which IIRC you can disable.
This is correct. Unfortunately, if you disable the MRC cache you will lose functionality like the ability to resume from S3 suspend, and your boot time will go up between 300ms and 30 some seconds, depending on the chipset you are looking at.
Stefan
Whether there is also something else writing to the chip from coreboot I'm not 100% but others will chime in on that, I'm sure.
Kind Regards,
John.
On 27/02/17 08:15, Naveed Ghori wrote:
Hi all, Does Coreboot write to the flash chip it resides on? Can this be disabled? Verify of the SPI bios chip fails once the unit has booted up at least once. � Best Regards, Naveed Naveed Ghori | Lead Firmware & Driver Engineer DTI Group Ltd | Transit Security & Surveillance 31 Affleck Road, Perth Airport, Western Australia 6105, Australia P +61 8 9373 2905,151 | F +61 8 9479 1190 |�naveed.ghori@dti.com.au Visit our website��www.dti.com.au The information contained in this email is confidential. If you receive this email in error, please inform DTI Group Ltd via the above contact details. If you are not the intended recipient, you may not use or disclose the information contained in this email or attachments.
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Thanks all for your suggestions. I do have fast boot enabled (and probably MRC cache too). I will try to disable that.
Main issue was that we have had a unit not boot up at all and a unit not boot up properly (as in Windows logo would fade in and out but stay in that state without progressing).
Both issues were fixed by writing the same bios (using a programmer or if the system would boot) or flashrom. This write should however remove anything written by the system on first boot. This makes me think that the cache or whatever else is writing to the flash chip is causing the system to fail.
I will test and update once I know if it was the MRC writing to the flash. Regards, Naveed
It was the MRC cache. :) One issue however with disabling the cache is that we get a long 20-30s beep (annoyingly loud :)) on shutdown. Any idea why as it doesn't seem to do this with the MRC cache turned off.
I might start a new thread for this depending on response. Cheers, And again Thanks for the help in this regard.
-----Original Message----- From: Naveed Ghori Sent: Tuesday, 28 February 2017 9:59 AM To: coreboot@coreboot.org Subject: RE: [coreboot] SPI Flash Writeprotect
Thanks all for your suggestions. I do have fast boot enabled (and probably MRC cache too). I will try to disable that.
Main issue was that we have had a unit not boot up at all and a unit not boot up properly (as in Windows logo would fade in and out but stay in that state without progressing).
Both issues were fixed by writing the same bios (using a programmer or if the system would boot) or flashrom. This write should however remove anything written by the system on first boot. This makes me think that the cache or whatever else is writing to the flash chip is causing the system to fail.
I will test and update once I know if it was the MRC writing to the flash. Regards, Naveed
Haven't the faintest idea, Naveed - have never tried running with the cache disabled. Only thing I can tell you is that if the cache is enabled, but not working for some reason, I didn't get such a beep.
I'm hoping one of the proper guys will have an idea about this.
Cheers,
John.
On 02/03/17 07:34, Naveed Ghori wrote:
It was the MRC cache. :) One issue however with disabling the cache is that we get a long 20-30s beep (annoyingly loud :)) on shutdown. Any idea why as it doesn't seem to do this with the MRC cache turned off.
I might start a new thread for this depending on response. Cheers, And again Thanks for the help in this regard.
-----Original Message----- From: Naveed Ghori Sent: Tuesday, 28 February 2017 9:59 AM To: coreboot@coreboot.org Subject: Re: [coreboot] SPI Flash Writeprotect
Thanks all for your suggestions. I do have fast boot enabled (and probably MRC cache too). I will try to disable that.
Main issue was that we have had a unit not boot up at all and a unit not boot up properly (as in Windows logo would fade in and out but stay in that state without progressing).
Both issues were fixed by writing the same bios (using a programmer or if the system would boot) or flashrom. This write should however remove anything written by the system on first boot. This makes me think that the cache or whatever else is writing to the flash chip is causing the system to fail.
I will test and update once I know if it was the MRC writing to the flash. Regards, Naveed
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John Lewis -
Marshall Dawson -
Naveed Ghori -
Stefan Reinauer