It's probably the MRC cache...
Agreed, if this feature is enabled it will reliably modify the flash contents during the first boot.  This can typically be disabled under the chipset menu.  You may need to look for something like "Enable Fast Boot" but I suspect this text could be inconsistent across technologies.

The Intel ME can also modify the contents without your knowledge, e.g. for logging.  This could potentially be more intermittent, though.  For good measure, you probably want to use the Intel FITC tool and ensure ME logging is disabled on your system.  (This is NDA only, I believe.)

Since you didn't mention your CPU vendor, the AMD PSP can also modify the flash device contents in its firmware area.

Of course, if you can read the device and identify the address of the change, that will give you clues for determining how it's getting modified.

Thanks,
Marshall


On Mon, Feb 27, 2017 at 2:38 AM, John Lewis <jlewis@johnlewis.ie> wrote:

Hi Naveed,

It's probably the MRC cache or something like that, which IIRC you can disable. Whether there is also something else writing to the chip from coreboot I'm not 100% but others will chime in on that, I'm sure.

Kind Regards,

John.


On 27/02/17 08:15, Naveed Ghori wrote:

Hi all,

Does Coreboot write to the flash chip it resides on? Can this be disabled?

Verify of the SPI bios chip fails once the unit has booted up at least once.

 

Best Regards,

Naveed

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