On Mon, Aug 26, 2013 at 12:47 PM, David Hendricks dhendrix@google.comwrote:
On Mon, Aug 26, 2013 at 1:13 AM, Patrick Georgi patrick@georgi-clan.dewrote:
Am 26.08.2013 09:12, schrieb Mohit Gupta:
After that I get stuck completely mainly because of RAM initialization steps as per JEDEC. I am looking for resources or tutorials which can point to me in right direction as to how read SPD info and use that to configure or initialize RAM module.
Memory initialization varies a lot by the standard (DDR2 vs DDR3, for example), and - when looking at it from the point of view of a firmware implementer - also by the chipset that drives the memory. For example the VIA chipsets with DDR3 support seem to do many things by itself that must be handled explicitely by initialization code on other chipsets.
I find our RAM init code for older Intel chipsets quite readable. But I'm probably biased because I was part of the development teams for that code.
You can find it at src/northbridge/i945 (driving DDR2) and src/northbridge/gm45 (DDR3) in our source tree. http://www.coreboot.org/Git describes how to access the source code.
As Patrick pointed out, it is quite specific to the hardware you are working on. And unfortunately documentation is scarce. Fortunately AMD publishes a good deal of info about their DRAM controller init in their BIOS and Kernel Developer's Guides (BKDG). Section 2.9.7 of the Family 16h BKDG sheds some light on the steps involved: http://developer.amd.com/resources/documentation-articles/developer-guides-m...
And on that note, you can peruse the sources here: http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/vendorcode/amd...
However I didn't work on that code so I have no idea how closely it resembles the manual. It might be better to start with the Exynos code as it much simpler and more self-contained. Then as you familiarize yourself with some common terminology you can dig into the more sophisticated AMD Northbridge code. Ctags are your friend, BTW.
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David Hendricks