Am 26.08.2013 09:12, schrieb Mohit Gupta:
After that I get stuck completely mainly because of
steps as per JEDEC. I am looking for resources or tutorials which can
point to me in right direction as to how read SPD info and use that to
configure or initialize RAM module.
Memory initialization varies a lot by the
standard (DDR2 vs DDR3, for
example), and - when looking at it from the point of view of a firmware
implementer - also by the chipset that drives the memory. For example
the VIA chipsets with DDR3 support seem to do many things by itself that
must be handled explicitely by initialization code on other chipsets.
I find our RAM init code for older Intel chipsets quite readable. But
I'm probably biased because I was part of the development teams for that
You can find it at src/northbridge/i945 (driving DDR2) and
src/northbridge/gm45 (DDR3) in our source tree.
describes how to access the source code.
I also don't know if I am allowed to post such
queries or if this
mailing list is only for advanced level users.
There are no requirements for
participating in the coreboot community
beyond common courtesy. Given the rather special topic we cover it helps
to be curious in the lower levels of computer technology (and coreboot
development in particular, but there are many people here whose
interests are on a tangent to that), and it helps to be willing to
research topics autonomously to some degree since this is a community of