Would an Ivybridge CPU even be expected to work with RDIMMs? Was this something anticipated when native raminit was written?
-Matt
On Mon, Sep 6, 2021 at 6:00 PM Michał Żygowski michal.zygowski@3mdeb.com wrote:
Hi Matthew,
On 8/31/21 11:46 PM, Matt B wrote:
Hello Patrick,
Thank you very much for your reply!
From subsequent investigation it appears that the ECC lines of the 7010 SFF are indeed connected and Xeon CPUs can be made to work under the stock BIOS (and presumably under coreboot).
A minor side question I have: does the chipset on intel ivybridge platforms play a role in ECC support? It appears to me that the only components involved are the CPU, RAM DIMMs, and BIOS.
I have some good news for you.
- I can assure that ECC lines are connected between CPU and DIMMs on
7010/9010 DT schematics 2) I have successfully launched my OptiPlex 9010 SFF with a Xeon E3-1275 v2 and 4x 4GB UDIMMs non-ECC.
Unfortunately I haven't been able to launch the machine with ECC RDIMMs due to I/O latency overflow in the native raminit. Probably it will only work with unregistered DIMMs (which I will probably try soon) because registers on the DIMMs introduce higher latency. Maybe Patrick can shed some light on this raminit matter?
Best regards,
Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org