coreboot

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39654 discussions

Coreboot chat room
by Arne 23 Apr '23

23 Apr '23

Hi, I just created a XMPP chat room about coreboot on our public XMPP server and I would be happy to make it to an official coreboot chatroom. The server is running since 2,5 years and will stay online for at least the next years. Maybe you like to join. So the main question is, can I write in the chatroom description "official coreboot chatroom"? I would also offer the coreboot delevopers a free XMPP chat account on https://ocean.monocles.de/apps/registration/ or https://ocean.monocles.eu/apps/registration/ Thanks for your project and best regards, Arne

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[coreboot - Bug #141] GRUB payload hangs in HP Elitebooks
by Riku Viitanen 22 Apr '23

22 Apr '23

Issue #141 has been updated by Riku Viitanen. File 0005-at-keyboard-timeout.patch added Encountered this while porting Libreboot to 2560p and 9470m. Added a 200 ms timeout in keyboard_controller_wait_until_ready, and everything works fine on both machines now. I'll be contacting upstream. Patch attached for anyone curious. ---------------------------------------- Bug #141: GRUB payload hangs in HP Elitebooks https://ticket.coreboot.org/issues/141#change-1485 * Author: Iru Cai * Status: New * Priority: Normal * Assignee: Iru Cai * Start date: 2017-09-19 ---------------------------------------- There may be some problem when initializing the keyboard controller, but SeaBIOS payload works fine. Using GRUB payload directly or chainload GRUB payload with SeaBIOS will both hang the system. I modified GRUB and find it hangs in set_scancodes(void), when calling the first write_mode. After ``grub_outb (mode, KEYBOARD_REG_DATA);``, the ``keyboard_controller_wait_until_ready()`` function goes to an infinite loop. ~~~ write_mode (int mode) { unsigned i; for (i = 0; i < GRUB_AT_TRIES; i++) { grub_uint8_t ack; keyboard_controller_wait_until_ready (); grub_outb (0xf0, KEYBOARD_REG_DATA); keyboard_controller_wait_until_ready (); grub_outb (mode, KEYBOARD_REG_DATA); keyboard_controller_wait_until_ready (); ack = wait_ack (); if (ack == GRUB_AT_NACK) continue; if (ack == GRUB_AT_ACK) break; return 0; } return (i != GRUB_AT_TRIES); } ~~~ ---Files-------------------------------- seabios.log (31.5 KB) 0005-at-keyboard-timeout.patch (1.09 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Support Question: "overflow detected" error message on start up (boothole?)
by illuviadeoro＠tutanota.com 20 Apr '23

20 Apr '23

Please tell me who I should contact if the following support question should be directed elsewhere. I have a System 76 computer with coreboot installed. A fine print error message flashes that an "overflow" is detected and I think the file path has "grub" in it. Brief flash, can't see. Is this the boothole vulnerability? It is in the firmware or coreboot, not on a disk grub. I have multiple OS and the message appears independently of loading a particular hard disk, although I have Fedora with the community copr installed on my primary disk. Thanks!

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Re: About device tree in Coreboot
by Martin Roth 20 Apr '23

20 Apr '23

Absolutely, please feel free to comment on it in google docs. Anyone with the URL can comment. If you want to help write it or make changes beyond just commenting, email me off-list for edit access. Martin Apr 20, 2023, 14:33 by maximilian.brune(a)9elements.com: > Maybe it make sense to review that in the google docs? Since its quite a bit of documentation it would probably be easier to review and/or edit it in google docs until publishing on gerrit. We can of course also review it afterwards in gerrit but for the big part its probably easier to do it in google docs via comments and stuff. Just a thought though. > > Max > > Am Do., 20. Apr. 2023 um 19:59 Uhr schrieb Martin Roth via coreboot <> coreboot(a)coreboot.org> >: > >> Here's some devicetree documentation I started working on, but never published. >> >> https://docs.google.com/document/d/1_pEbupbU9K638uvN1qVNvweP5dP4KuunHWq1NBf… >> >> Sorry for the google docs link. I'll see what still needs to be done and push it to documentation folder. >> >> Martin >> >> Apr 17, 2023, 02:29 by >> michal.zygowski(a)3mdeb.com>> : >> >> > Dear Sir or Madam, >> > >> > On 11.04.2023 04:41, Chiang.Gain 江有舜 TAO wrote: >> > >> >> Dear Sir >> >> >> >> >> >> >> >> This is Inventec BIOS team, we are trying to port Coreboot to our Server Board >> >> which is based on Intel CRB ArcherCity. >> >> >> >> We have to add “Devicetree.cb” files under mainboard folder, right ? >> >> >> > >> > That's correct. >> > >> >> >> >> >> >> >> >> We had read the following files but we are still confused and don’t know how to >> >> modify those files to match our design. >> >> >> >> >> >> >> >> Documentation/getting_started/devicetree.md >> >> >> >> Documentation/drivers/dt_entries.md >> >> >> >> >> >> >> >> We would like to know if there are any training materials or further Docs; >> >> particular to “syntax”. >> >> >> >> that we can refer to. >> >> >> > >> > AFAIK there is no training for devicetree in particular. The links above are >> > already quite detailed and I doubt there are better materials than those as of >> > today. I advise to base your devicetree on archercity crb: >> > >> https://github.com/coreboot/coreboot/blob/master/src/mainboard/intel/archer… >> > >> > In short how it works: >> > >> > For Sapphire Rapids platform the final devicetree is a merge of >> > >> https://github.com/coreboot/coreboot/blob/master/src/soc/intel/xeon_sp/spr/… >> > and the mainboard's devicetree (the one you trying to create). >> > >> > As the chipset.cb defines all the default devices all you need to do in >> > mainboard's devicetree is to define the board-specific configuration. Each >> > devicetree starts with a chip declaration which has to point to a directory in >> > coreboot source that contains a chip.h file. This chips declaration must be a >> > soc directory, in your case "chip soc/intel/xeon_sp/spr". Each declaration must >> > be closed with an "end" word. Inside the scope of the chip you may place the >> > same declarations as in chipset.cb, but set it to your desired values. E.g. if >> > your design does not use PCIe root port 12 and 13, you can define the following: >> > >> > chip soc/intel/xeon_sp/spr >> > device domain 0 on >> > device pci 1a.0 off end # Intel device 1bb4: PCH PCIe Root Port #12 >> > device pci 1b.0 off end # Intel device 1bb5: PCH PCIe Root Port #13 >> > end >> > end >> > >> > What is important is to keep the scopes intact. One may disable the device by >> > changing "on" to "off". if you would like to override the soc-specific >> > configuration, then you need to look at >> > >> https://github.com/coreboot/coreboot/blob/master/src/soc/intel/xeon_sp/spr/… >> > The entries in devicetree starting with "register" declaration means you want to >> > set a variable defined in chip.h for given chip/soc. And for example if you >> > would like to configure a board specific TCC activation offset (aka CPU >> > throttling thermal threshold), you would need to add the following: >> > >> > >> > chip soc/intel/xeon_sp/spr >> > >> > register "tcc_offset" = "10" >> > >> > device domain 0 on >> > device pci 1a.0 off end # Intel device 1bb4: PCH PCIe Root Port #12 >> > device pci 1b.0 off end # Intel device 1bb5: PCH PCIe Root Port #13 >> > end >> > end >> > >> > The offset is relative to TJmax and the threshold would be TJmax - tcc_offset. >> > >> > I could write a whole essay what you can do with devicetree. It is hard to >> > explain all possibilities in one mail, it would be great if you could be more >> > specific about the problems you have, given that you haven't given any info >> > about your hardware. The devicetree contents are specific to given board design >> > and they may even require implementing new drivers which have to be referenced >> > in the devicetree. Also it may be worth considering coreboot consulting >> > services: >> https://www.coreboot.org/consulting.html >> > This page: >> https://doc.coreboot.org/distributions.html >> > should also give you an overview who is doing coreboot work and ships coreboot >> > on their devices. >> > >> >> >> >> >> >> >> >> Any kind of helps are appreciated. >> >> >> >> >> >> >> >> Thanks >> >> >> >> >> >> >> >> Gain >> >> >> >> >> >> >> >> >> >> >> >> >> >> -------------------------------------------------------------------------------- >> >> >> >> *Confidentiality Note* >> >> 本郵件含有英業達股份有限公司機密資訊、或受法律保護之資料，唯有原發信人指定之收信 >> >> 人得閱讀或使用本郵件之內容。如您並非被指定之收信人，請立即將本郵件及所有附件予以 >> >> 刪除；請勿揭露、儲存或使用本郵件之任何資訊，並請您立即告知原發信人本郵件的傳遞錯 >> >> 誤。謝謝您的合作。 >> >> This e-mail transmission and any attachments contain information from Inventec >> >> Corporation. The information is confidential and/or privileged and intended to >> >> be solely for the use of the individuals or entities named in this e-mail >> >> transmission. If you are not the intended recipient, be aware that any >> >> disclosure, saving or use of the content of this e-mail transmission and >> >> attachments is strictly prohibited. If you have received this email transmission >> >> in error, please notify us immediately, and delete the e-mail and attachments. >> >> We greatly appreciate your cooperation. >> >> >> >> _______________________________________________ >> >> coreboot mailing list -- >> coreboot(a)coreboot.org >> >> To unsubscribe send an email to >> coreboot-leave(a)coreboot.org >> >> >> > >> > Best regards, >> > -- >> > Michał Żygowski >> > Firmware Engineer >> > GPG: 6B5BA214D21FCEB2 >> > >> https://3mdeb.com>> | @3mdeb_com >> > >> >> _______________________________________________ >> coreboot mailing list -- >> coreboot(a)coreboot.org >> To unsubscribe send an email to >> coreboot-leave(a)coreboot.org >>

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[coreboot - Bug #440] superiotool tells you to run it as root and stops even when ran as root
by Nicholas Chin 20 Apr '23

20 Apr '23

Issue #440 has been updated by Nicholas Chin. I found this comment on this GitHub issue, which might explain the strange behaviour we are seeing: https://github.com/zamaudio/intelmetool/issues/20#issuecomment-751562837 > I got this error too, and tracked the issue down. > > iopl() returns an error EPERM (Operation not permitted) - even when invoked as root - if the kernel is in "lockdown mode". One of the things that lockdown mode does is disables userspace access to privileged I/O. > > You can check if you are in lockdown mode as follows: > > $ cat /sys/kernel/security/lockdown none [integrity] confidentiality > > Modern Linux distributions - such as Debian, in my case - will automatically enter lockdown mode (integrity) when the kernel is booted with EFI Secure Boot enabled. To fix the issue I simply disabled Secure Boot and restarted my machine. Could you check if your system is in lockdown mode and if you have secure boot enabled? ---------------------------------------- Bug #440: superiotool tells you to run it as root and stops even when ran as root https://ticket.coreboot.org/issues/440#change-1484 * Author: J Nky * Status: Response Needed * Priority: Normal * Target version: none * Start date: 2022-11-24 * Affected versions: 4.15 * Affected OS: ubuntu 22.10 ---------------------------------------- On ubuntu 22.10: **sudo superiotool** iopl: Function not implemented Superiotool must be run as root. superiotool tells you to run it as root and stops even when ran as root -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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About device tree in Coreboot
by Chiang.Gain 江有舜 TAO 20 Apr '23

20 Apr '23

Dear Sir This is Inventec BIOS team, we are trying to port Coreboot to our Server Board which is based on Intel CRB ArcherCity. We have to add “Devicetree.cb” files under mainboard folder, right ? We had read the following files but we are still confused and don’t know how to modify those files to match our design. Documentation/getting_started/devicetree.md Documentation/drivers/dt_entries.md We would like to know if there are any training materials or further Docs; particular to “syntax”. that we can refer to. Any kind of helps are appreciated. Thanks Gain ________________________________ Confidentiality Note 本郵件含有英業達股?有限公司機密資訊、或受法律保護之資料，唯有原發信人指定之收信人得?讀或使用本郵件之?容。如?並非被指定之收信人，請立即將本郵件及所有附件予以刪除；請勿?露、儲存或使用本郵件之任何資訊，並請?立即告知原發信人本郵件的傳遞錯誤。謝謝?的合作。 This e-mail transmission and any attachments contain information from Inventec Corporation. The information is confidential and/or privileged and intended to be solely for the use of the individuals or entities named in this e-mail transmission. If you are not the intended recipient, be aware that any disclosure, saving or use of the content of this e-mail transmission and attachments is strictly prohibited. If you have received this email transmission in error, please notify us immediately, and delete the e-mail and attachments. We greatly appreciate your cooperation.

4 3

Request for comments on removing NE2000 console support
by Martin Roth 20 Apr '23

20 Apr '23

The NE2000 was a fantastic card back in its day, but as far as I can tell, that day is long past. Is anyone using this feature? Does it make sense to keep it in the master branch? The code, as far as I can tell, is not problematic, but I also don't know whether or not it's still working. Its implementation really only consists of two files plus sections of Kconfig and a Makefile. If it's not being used anymore, I'd like to propose that we remove the NE2000 console support from the master branch. If it is being used by anyone, there's a request to update the description in src/console/Kconfig. Thanks everyone. Martin

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coreboot 4.20 release scheduled for May 1, 2023
by Martin Roth 20 Apr '23

20 Apr '23

Hi All, When we did the last release, we had hoped to be able to get the 4.20 release out today (4/20 in the US). Unfortunately, the release team was not ready, so the release has been pushed out to 5/1. As always, please test any boards, and give feedback. We'll include any known issues from the bug tracker in the release notes going forward, so please file bugs if there are any issues. Please mark any commits that you specifically want to go into the release with the `coreboot_release_4.20` hashtag. If you're not familiar with hashtags, you can set them by clicking the "show all" button at the top left of the screen in gerrit, then clicking the "hastags" edit icon. It's recommended to avoid merging any heavy new features between now and the release date. If there are any obsolete code paths that should be removed in 6 months, please bring them up in the mailing list now. Current statistics since the 4.19 release: - Total Commits: 1273 - Average Commits per day: 13.49 - Total lines added: 85872 - Total lines removed: 30755 - Number of patches adding more than 100 lines: 109 - Total difference between added and removed: 55117 - Total authors: ~150 - New authors: ~25 Added 22 mainboards: ------------------- * ASROCK B75M-ITX * Dell Inc. Latitude E6400 * Google Aurash * Google Constitution * Google Hades * Google Myst * Google Screebo * Google Starmie * Google Taranza * Google Uldren * Google Yavilla * HP EliteBook 2170p * Intel Archer City CRB * Intel DQ67SW * Intel Meteorlake-P RVP with Microchip EC * Protectli VP2420 * Protectli VP4630/VP4650 * Protectli VP4670 * Siemens MC_EHL4 * System76 lemp11 * System76 oryp10 * System76 oryp9 Removed 3 mainboards: ------------------- * Intel Icelake U DDR4/LPDDR4 RVP * Intel Icelake Y LPDDR4 RVP * Scaleway TAGADA Added 2 socs: ------------------- * src/soc/intel/xeon_sp/ebg * src/soc/intel/xeon_sp/spr Removed 1 socs: ------------------- * src/soc/intel/icelake

1 0

Working X11SSH-F config
by Martin Kjær Jørgensen 20 Apr '23

20 Apr '23

Hello, I have recently started experimenting with coreboot so please forgive my ignorance :-) I can make it boot using edk2 payload and only flashing "bios" region and I am able to make an ordinary linux distro boot. Using OEM BIOS from supermicro everything seems to work as expected, but using my coreboot image I run into the following issues: 1. I also get PCI related errors and warnings during coreboot boot. 2. Microcode update errors during coreboot boot, although it claims microcode to be updated afterwards. 3. My mainboard have 2 Intel NICs but Linux kernel claims only 1 exists, and lspci only shows 1. The "first" one :-) . 4. Coreboot does not show up, or work, if BMC is not enabled using the jumper. 5. When Linux issues system reset, machine freeze and needs to be manually powered off. If issuing "power off" the machine powers off as normal. Have anyone got a fully "working"/"stable" config for their X11SSH-* board I can use as reference? I got the feeling I'm missing something obvious or needed tweaks ... /Martin

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Is my PC compatible with the Coreboot bios?
by Cédric LACHAUD 18 Apr '23

18 Apr '23

Hello, I am contacting you because a year and a few months ago, I bought a PC assembled by the company NovaCustom (model NH77) and I would like to know if I can install Coreboot as a BIOS without risk for my PC. I specify that I did not find the "official" name of my motherboard (which is, according to my current BIOS - InsydeH20 - NH5x_7xDPx). When I go to my Windows 11 (in the msinfo32 tool), the manufacturer of my motherboard would be "Notebook". Here is the result of the commands you wanted to be addressed for any such questions: * lspci -tvnn -[0000:00]-+-00.0 Intel Corporation 10th Gen Core Processor Host Bridge/DRAM Registers [8086:9b54] +-01.0-[01-05]--+-00.0 NVIDIA Corporation GA106M [GeForce RTX 3060 Mobile / Max-Q] [10de:2520] | \-00.1 NVIDIA Corporation Device [10de:228e] +-02.0 Intel Corporation CometLake-H GT2 [UHD Graphics] [8086:9bc4] +-12.0 Intel Corporation Comet Lake PCH Thermal Controller [8086:06f9] +-14.0 Intel Corporation Comet Lake USB 3.1 xHCI Host Controller [8086:06ed] +-14.2 Intel Corporation Comet Lake PCH Shared SRAM [8086:06ef] +-15.0 Intel Corporation Comet Lake PCH Serial IO I2C Controller #0 [8086:06e8] +-15.1 Intel Corporation Comet Lake PCH Serial IO I2C Controller #1 [8086:06e9] +-16.0 Intel Corporation Comet Lake HECI Controller [8086:06e0] +-17.0 Intel Corporation Device [8086:06d3] +-1b.0-[06]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808] +-1d.0-[07]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808] +-1d.5-[08]----00.0 Intel Corporation Wi-Fi 6 AX200 [8086:2723] +-1d.6-[09]--+-00.0 Realtek Semiconductor Co., Ltd. RTL8411B PCI Express Card Reader [10ec:5287] | \-00.1 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1f.0 Intel Corporation Comet Lake LPC Controller [8086:068d] +-1f.3 Intel Corporation Comet Lake PCH cAVS [8086:06c8] +-1f.4 Intel Corporation Comet Lake PCH SMBus Controller [8086:06a3] \-1f.5 Intel Corporation Comet Lake PCH SPI Controller [8086:06a4] * superiotool -dV superiotool r4.19-1262-g03232e93d3 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Aspeed Super I/O at 0x2e... Found Aspeed AST2400 (id=0x00) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 55 70 02 01 00 00 00 00 00 00 00 00 01 00 12 03 def 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x02 (SUART1) idx 30 60 61 70 71 f0 val 00 02 f8 03 02 00 def 00 03 f8 04 02 RR LDN 0x03 (SUART2) idx 30 60 61 70 71 f0 val 00 00 00 00 00 00 def 00 02 f8 03 02 00 LDN 0x04 (SWC) idx 30 60 61 62 63 64 65 66 67 70 71 val 00 00 00 00 00 00 00 00 00 00 01 def 00 08 e6 08 e0 08 e4 08 e8 09 01 LDN 0x05 (Keyboard config (KBC)) idx 30 60 61 62 63 70 71 72 73 f0 val 01 00 00 00 00 0c 01 00 00 00 def 00 00 60 00 64 01 02 0c 02 83 LDN 0x07 (GPIO) idx 30 38 70 71 val 00 00 00 00 def 00 00 0b 01 LDN 0x0b (SUART3) idx 30 60 61 70 71 f0 val 00 00 00 00 00 00 def 00 03 e8 06 02 00 LDN 0x0c (SUART4) idx 30 60 61 70 71 f0 val 00 00 00 00 00 00 def 00 02 e8 05 02 00 LDN 0x0d (iLPC2AHB) idx 30 70 71 f0 f1 f2 f3 f4 f5 f6 f7 f8 fe val 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 09 01 NA NA NA NA NA NA NA NA 00 00 LDN 0x0e (Mailbox) idx 30 60 61 70 71 val 00 00 00 00 00 def 00 08 c0 09 01 Probing for Aspeed Super I/O at 0x4e... Failed. Returned data: scratch registers all read as 0xff Probing for Exar Super I/O at 0x2e... Failed. Returned data: vid=0x0001, id=0x7055 Probing for Exar Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0001, id=0x7055 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0001, id=0x7055 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT5570E (id=0x5570, rev=0x2) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2d val 55 70 02 01 00 00 00 00 00 00 00 00 00 def 55 70 NA 01 RR 00 00 RR RR RR RR RR 00 LDN 0x01 (Serial Port 1 (UART1)) idx 30 60 61 62 63 70 71 f0 val 00 03 f8 00 00 04 02 00 def 00 02 f8 00 00 03 02 00 LDN 0x02 (Serial Port 2 (UART2)) idx 30 60 61 62 63 70 71 f0 val 00 02 f8 00 00 03 02 00 def 00 02 f8 00 00 03 02 00 LDN 0x04 (System Wake-Up Control (SWUC)) idx 30 60 61 70 71 val 00 00 00 00 01 def 00 00 00 00 01 LDN 0x05 (KBC Mouse) idx 30 70 71 val 01 0c 01 def 00 0c 01 LDN 0x06 (KBC Keyboard) idx 30 60 61 62 63 70 71 val 01 00 60 00 64 01 01 def 00 00 60 00 64 01 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 71 val 00 03 10 00 02 def 00 03 10 00 02 LDN 0x0f (Shared Memory/Flash Interface (SMFI)) idx 30 60 61 70 71 f0 f1 f2 f3 f4 f5 f6 f9 fa fb fc val 01 00 00 00 02 fe 70 00 00 09 00 70 00 00 00 00 def 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 01 LDN 0x10 (RTC-like Timer (RTC)) idx 30 60 61 62 63 64 65 66 67 68 69 70 71 f0 f1 f2 f3 f4 f5 val 01 00 94 05 00 00 00 00 00 00 00 00 01 00 49 4a 00 3f 3f def 00 00 70 02 72 00 00 00 00 00 00 08 01 00 49 4a 00 00 00 LDN 0x11 (Power Management Interface Channel 1 (PMC1)) idx 30 60 61 62 63 70 71 val 01 00 62 00 66 00 01 def 00 00 62 00 66 01 01 LDN 0x12 (Power Management Interface Channel 2 (PMC2)) idx 30 60 61 62 63 64 65 70 71 f0 val 00 00 68 00 6c 00 00 00 01 00 def 00 00 68 00 6c 00 00 01 01 NA LDN 0x13 (Serial Peripheral Interface (SSPI)) idx 30 60 61 70 71 val 00 03 00 00 02 def 00 03 00 00 02 LDN 0x14 (Platform Environment Control Interface (PECI)) idx 30 60 61 val 00 00 00 def 00 00 00 LDN 0x17 (Power Management Interface Channel 3 (PMC3)) idx 30 60 61 62 63 70 71 val 00 00 6a 00 6e 01 01 def 00 00 6a 00 6e 01 01 LDN 0x18 (Power Management Interface Channel 4 (PMC4)) idx 30 60 61 62 63 70 71 val 00 00 74 00 78 01 01 def 00 00 74 00 78 01 01 LDN 0x19 (Power Management Interface Channel 5 (PMC5)) idx 30 60 61 62 63 70 71 val 00 00 7a 00 7c 01 01 def 00 00 7a 00 7c 01 01 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: sid=0x55, srid=0x00 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0x5570 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0x55, id=0x5570, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x55, rev=0x70 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0x55/0x00, rev=0x70 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0x55/0x00, rev=0x70 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0x55/0x00, rev=0x70 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0x55/0x00, rev=0x70 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x55, rev=0x70 Probing for VIA Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=vt82c686) at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0x5570, rev=0x00 Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0x55, rev=0x70 Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff * flashrom -p internal -V flashrom v1.2 on Linux 6.2.6-76060206-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.7.0, GCC 11.2.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer get_mtd_info: device_name: "BIOS", is_writeable: 0, numeraseregions: 0, total_size: 16777216, erasesize: 4096 Cannot open file stream for /dev/mtd0 No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 55. WARNING: No chipset found. Flash detection will most likely fail. ======================================================================== You may be running flashrom on an unknown laptop. We could not detect this for sure because your vendor has not set up the SMBIOS tables correctly. Some internal buses have been disabled for safety reasons. You can enforce using all buses by adding -p internal:laptop=this_is_not_a_laptop to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and https://flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== The following protocols are supported: None. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. My PC has an Intel i7-10750H processor, an NVidia GeForce RTX 3060 graphics card, 64 GB of RAM: Getting SMBIOS data from sysfs. SMBIOS 3.2.0 present. Handle 0x001C, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: No Error Number Of Devices: 2 Handle 0x001D, DMI type 17, 84 bytes Memory Device Array Handle: 0x001C Error Information Handle: No Error Total Width: 64 bits Data Width: 64 bits Size: 32 GB Form Factor: SODIMM Set: None Locator: ChannelA-DIMM0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 2933 MT/s Manufacturer: Kingston Serial Number: B5766329 Asset Tag: 9876543210 Part Number: 9905744-066.A00G Rank: 2 Configured Memory Speed: 2933 MT/s Minimum Voltage: 1.25 V Maximum Voltage: 1.5 V Configured Voltage: 1.2 V Memory Technology: DRAM Memory Operating Mode Capability: Volatile memory Firmware Version: Not Specified Module Manufacturer ID: Bank 2, Hex 0x98 Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: 32 GB Cache Size: None Logical Size: None Handle 0x001E, DMI type 17, 84 bytes Memory Device Array Handle: 0x001C Error Information Handle: No Error Total Width: 64 bits Data Width: 64 bits Size: 32 GB Form Factor: SODIMM Set: None Locator: ChannelB-DIMM0 Bank Locator: BANK 2 Type: DDR4 Type Detail: Synchronous Speed: 2933 MT/s Manufacturer: Kingston Serial Number: C8B67CA0 Asset Tag: 9876543210 Part Number: 9905744-066.A00G Rank: 2 Configured Memory Speed: 2933 MT/s Minimum Voltage: 1.25 V Maximum Voltage: 1.5 V Configured Voltage: 1.2 V Memory Technology: DRAM Memory Operating Mode Capability: Volatile memory Firmware Version: Not Specified Module Manufacturer ID: Bank 2, Hex 0x98 Module Product ID: Unknown Memory Subsystem Controller Manufacturer ID: Unknown Memory Subsystem Controller Product ID: Unknown Non-Volatile Size: None Volatile Size: 32 GB Cache Size: None Logical Size: None Thank you in advance for your attention to my message. Yours sincerely, LACHAUD Cédric

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