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39654 discussions

How to build UEFI payload for Coreboot?
by Sarawadi, Ravishankar 15 Jun '23

15 Jun '23

Is EDK2/Tianocore payload not supported for coreboot on latest tip? Any build and interation steps for how-to for UEFI payload on top of coreboot? Thanks, -Ravi

2 3

Builds of Google boards fail due to FSP size
by Felix Singer 08 Jun '23

08 Jun '23

Hello, Moving forward the submodule pointers of the microcode [1] or Intel FSP [2][3] repository will make the Google boards (ChromeOS builds?) failing because the FSP does not fit into their flash region anymore. How do we deal with that issue? I think there are two options: * Make the flash regions bigger * Disable ChromeOS builds for upstream Best Felix --- [1] https://review.coreboot.org/c/coreboot/+/75631 [2] https://review.coreboot.org/c/coreboot/+/74242 [3] https://review.coreboot.org/c/coreboot/+/74442

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Erying Tigerlake HM570 Micro-ATX motherboard S3 memory power gate..
by Timothy Potter 08 Jun '23

08 Jun '23

I've been looking at the work being done here https://github.com/ellyq/coreboot to get coreboot as an alternative to Erying's flaky BIOS. I'm particularly interested in getting S3 suspend working. From what I can see, the motherboard suspends correctly, but doesn't maintain power to the DRAM, so resets when it resumes. Given Erying won't provided schematics for the motherboard, is there any other way to work out how to "gate" the DRAM power reset signal? I assume it's controlled by a GPIO pin on the PCH/CPU. Are there standard pin assignments for these signals? I see some references to it in the codebase with respect to Lenovo using a different pin. Thanks, Tim.

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Re: Builds of Google boards fail due to FSP size
by Subrata Banik 08 Jun '23

08 Jun '23

HI Paul and Team, I guess there is some kind of miscommunication between the usage of FSP blobs by the Google team for ChromeOS devices that Intel share via their GitHub repo. I didn't check. As Subrata explained in his comments[1], Google seems > to use some sort of customized FSP binary, which is built from an > internal repository and also stripped. So I was thinking that might be > the reason for that issue, because related ChromeOS flashmaps are > optimized for their FSP binary and not for the one from the public > Intel repo. Let me clarify, the changes that I have mentioned in my blog post earlier is done in context of Alder Lake (Brya variant devices) to optimize the FSP blobs (a post processing of the FSP blobs) but it doesn't mean that we have optimized the ChromeOS FMD (SPI layout) to take advantage of the optimized FSP blobs. Please take a look into the "chromeos.fmd" file history. https://github.com/coreboot/coreboot/commits/master/src/mainboard/google/br… We need to check why the updated FSP blob is breaking the ChromeOS devices but as mentioned above the FSP binary that we are using from Intel release source GitHub and we haven't limited the SPI layout to encash those savings yet. Let me know if you are looking for some clarification. Thanks, Subrata > > > From: Felix Singer <felixsinger(a)posteo.net> > Date: Wed, Jun 7, 2023 at 4:56 PM > Subject: [coreboot] Re: Builds of Google boards fail due to FSP size > To: Paul Menzel <pmenzel(a)molgen.mpg.de>, <coreboot(a)coreboot.org> > > > Hi Paul, > > On Wed, 2023-06-07 at 08:09 +0200, Paul Menzel wrote: > > Excuse my ignorance. How can all Google boards fail? Aren’t there > > Intel hardware generations where FSP should not be updated anymore? > > I was unclear, sorry. Only the Alderlake boards are affected as it > seems. > > > > Also, how much space is missing? Why did FSP grow that much? > > I didn't check. As Subrata explained in his comments[1], Google seems > to use some sort of customized FSP binary, which is built from an > internal repository and also stripped. So I was thinking that might be > the reason for that issue, because related ChromeOS flashmaps are > optimized for their FSP binary and not for the one from the public > Intel repo. > > > > Could a third option be to ask the FSP folks to provide smaller > > blobs? > > I don't know how feasible that is. From recent discussions about > releasing FSP binaries, it's even a thing to get *any* FSP binary > uploaded on the FSP repo. > > However, I think the best compromise is the one I wrote in my second > mail, which is to use only the FSP headers from the repo but not the > binaries for ChromeOS builds. Customized binaries can still be added by > the build system or manually. > > For the coreboot CI it shouldn't make much difference (probably not > anything?) because it does only build-tests and there are still enough > other boards to build-test that part. > > > Best > > Felix > > --- > [1] https://review.coreboot.org/c/coreboot/+/74442 > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org >

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Question on coreboot with grub4dos legacy and UEFI?
by Michael D. Setzer II 06 Jun '23

06 Jun '23

Have a project G4L that does disk imaging. Just released a new version and have a user that downloaded it, but fails to boot on his laptop with coreboot?? The image file contains both the grub4dos legacy boot loader, and the grub4dos efi boot loader. Works fine on my systems, and with virtual box as well. Does not support secure boot, since kernels are not blessed with Microsoft certificates. Not sure if there is something that would need to be done to get it to work with grub4dos? Project is on sourceforge?? +------------------------------------------------------------+ Michael D. Setzer II - Computer Science Instructor (Retired) mailto:mikes@guam.net mailto:msetzerii@gmail.com Guam - Where America's Day Begins G4L Disk Imaging Project maintainer http://sourceforge.net/projects/g4l/ +------------------------------------------------------------+

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New on blogs.coreboot.org: coreboot versions 4.20 and 4.20.1 have been released
by blogs.coreboot.org 04 Jun '23

04 Jun '23

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Planned maintenance on ticket.coreboot.org on July 1st
by Felix Singer 01 Jun '23

01 Jun '23

I will do some maintenance work on our ticket system on July 1st, which is the upcoming Thursday. The maintenance will * start at 9:00 am UTC+0 * end at 11:00 am UTC+0 (estimated, probably at latest) During this time, the ticket system will be down and/or unusable. I will announce as soon as the work is finished. The maintenance will cover: * Updating the system to the newest stable release * Updating the ticket system to the newest stable release Felix

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[coreboot - Other #492] (New) Evaluate changes need to be made to support Intel's X86S ISA changes
by Martin Roth 28 May '23

28 May '23

Issue #492 has been reported by Martin Roth. ---------------------------------------- Other #492: Evaluate changes need to be made to support Intel's X86S ISA changes https://ticket.coreboot.org/issues/492 * Author: Martin Roth * Status: New * Priority: Normal * Category: coreboot common code * Target version: none * Start date: 2023-05-28 ---------------------------------------- This past week, Intel announced a plan to boot directly to 64-bit mode[1]. While the timeline released with the announcement does't have any dates for the implementation, due to the huge impact this will have on coreboot, it seems appropriate to start looking at what changes will need to be made to support these changes to the ISA. Changes currently listed: Changes in X86-S ISA consist of: - restricting the CPU to be always in paged mode - removing 32-bit ring 0, as well as vm86 mode. - removing ring 1 and ring 2 - removing 16-bit real and protected modes - removing 16-bit addressing - removing fixed MTRRs - removing user-level I/O and string I/O - removing CR0 Write-Through mode - removing legacy FPU control bits in CR0 - removing ring 3 interrupt flag control - removing obsolete CR access instruction - rearchitecting INIT/SIPI - adding a new mechanism to switch between 4- and 5-level page tables - removing XAPIC and only supporting x2APIC - removing APIC support for 8529 - removing the disabling of NX or SYSCALL or long mode in the EFER MSR - removing the #SS and #NP exceptions - supporting a subset of segmentation architecture, with the following conditions: o restricted to a subset of IDT event delivery o base only for FS, GS o base and limit for GDT, IDT, and TSS o no limit on data or code fetches in 32-bit mode (similar to 64-bit) o no AR or unusable selector checking on CS, DS, ES, FS, and GS on data or code fetches in any mode o restricted support for far call, far return, far jump, and IRET (like FRED). 1: https://web.archive.org/web/20230526070811/https://www.intel.com/content/ww… -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Looking to get Coreboot working on Jasper Lake / N5105 mini PC with 4x Intel 2.5Gbit NICs
by Marcos Scriven 25 May '23

25 May '23

Hello all I'd like to get Coreboot working on a new target device, so I'll follow the 6 steps in the https://www.coreboot.org/FAQ section entitled "Will coreboot work on my machine?" It looks like someone emailed the mailing list about this back in November '22 https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/I5HF…, but if I'm reading the archive correctly, didn't get any responses. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Board Vendor: Board is branded Topton, but the board is from CWWK. CWWK mentions this board on one of their firmware update pages https://www.changwang.com/down/74.html Board Name: MW-JSL2.5G4L CPU: N5105 North Bridge Intel Jasper Lake Host Bridge rev 00 South Bridge Intel Jasper Lake PCH rev 01 • Step 2: Linux "*lspci -tvnn*" output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[0000:00]-+-00.0 Intel Corporation Device [8086:4e24] +-02.0 Intel Corporation Device [8086:4e61] +-04.0 Intel Corporation Device [8086:4e03] +-14.0 Intel Corporation Device [8086:4ded] +-14.2 Intel Corporation Device [8086:4def] +-15.0 Intel Corporation Device [8086:4de8] +-15.2 Intel Corporation Device [8086:4dea] +-16.0 Intel Corporation Device [8086:4de0] +-17.0 Intel Corporation Device [8086:4dd3] +-19.0 Intel Corporation Device [8086:4dc5] +-19.1 Intel Corporation Device [8086:4dc6] +-1c.0-[01]----00.0 Phison Electronics Corporation E12 NVMe Controller [1987:5012] +-1c.4-[02]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.5-[03]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.6-[04]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.7-[05]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1e.0 Intel Corporation Device [8086:4da8] +-1e.3 Intel Corporation Device [8086:4dab] +-1f.0 Intel Corporation Device [8086:4d87] +-1f.3 Intel Corporation Device [8086:4dc8] +-1f.4 Intel Corporation Device [8086:4da3] \-1f.5 Intel Corporation Device [8086:4da4] • Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "*superiotool <https://www.coreboot.org/Superiotool> -dV*"). Output of superiotool -dV (minus all the probing/failed): Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 0c 40 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 01 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 80 00 00 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f7 80 08 d1 00 41 02 0a 10 0a 00 00 01 00 00 00 00 00 00 00 00 00 00 00 c0 03 01 06 80 48 90 00 00 00 00 00 00 b0 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 • Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "*flashrom <http://flashrom.org/> -p internal -V*" Direct inspection shows 8-pin 16MB w25q128jv, however, flashrom doesn't seem to include that in the list of Winbond chips it probes for. dmidecode says it's an 8MB ROM, so not sure why the discrepancy • Step 5: URL to the mainboard specifications page (optional). Topton (branded) https://www.aliexpress.com/item/1005004374464011.html Can't find official specs, but there's a pho • Step 6: Any other relevant information you can provide. There's a photo of the board on the left of this BIOS update page https://www-changwang-com.translate.goog/down/74.html?_x_tr_sl=zh-CN&_x_tr_… I've been Googling both "Jasperlake coreboot" and "n5105 coreboot". I see there was news of starting to support this back in January 2020 https://www.phoronix.com/news/Coreboot-JSP-TGL-Razer-ICL Looking at some Coreboot commits, I see a "jasperlake-rvp" target was added, so I simply tried it out. It seems to build fine, but with two warnings: ** WARNING ** ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP. The resulting image won't contain the FSP binaries and will not boot unless they are added later. ** WARNING ** coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. The first warning seems to suggest I can't ignore is (as it won't boot). I thus went looking for an FSP bin for this chip. Unfortunately it doesn't seem to be in the official Intel Github repo, and there's an unanswered issue there looking for it https://github.com/intel/FSP/issues/74 I hope that provides the necessary info to make a start! Thanks Marcos

2 3

Looking to get Coreboot working on Jasper Lake / N5105 mini PC with 4x Intel 2.5Gbit NICs
by Marcos Scriven 23 May '23

23 May '23

(This is a second attempt at posting - not heard back from mods, but so far as I can tell I'm a subscribe of this mail group) Hello all I'd like to get Coreboot working on a new target device, so I'll follow the 6 steps in the https://www.coreboot.org/FAQ section entitled "Will coreboot work on my machine?" It looks like someone emailed the mailing list about this back in November '22: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/I5HF…, but if I'm reading the archive correctly, didn't get any responses. Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Board Vendor: Board is branded Topton, but the board is from CWWK. CWWK mentions this board on one of their firmware update pages https://www.changwang.com/down/74.html Board Name: MW-JSL2.5G4L CPU: N5105 North Bridge Intel Jasper Lake Host Bridge rev 00 South Bridge Intel Jasper Lake PCH rev 01 • Step 2: Linux "*lspci -tvnn*" output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[0000:00]-+-00.0 Intel Corporation Device [8086:4e24] +-02.0 Intel Corporation Device [8086:4e61] +-04.0 Intel Corporation Device [8086:4e03] +-14.0 Intel Corporation Device [8086:4ded] +-14.2 Intel Corporation Device [8086:4def] +-15.0 Intel Corporation Device [8086:4de8] +-15.2 Intel Corporation Device [8086:4dea] +-16.0 Intel Corporation Device [8086:4de0] +-17.0 Intel Corporation Device [8086:4dd3] +-19.0 Intel Corporation Device [8086:4dc5] +-19.1 Intel Corporation Device [8086:4dc6] +-1c.0-[01]----00.0 Phison Electronics Corporation E12 NVMe Controller [1987:5012] +-1c.4-[02]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.5-[03]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.6-[04]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1c.7-[05]----00.0 Intel Corporation Ethernet Controller I225-V [8086:15f3] +-1e.0 Intel Corporation Device [8086:4da8] +-1e.3 Intel Corporation Device [8086:4dab] +-1f.0 Intel Corporation Device [8086:4d87] +-1f.3 Intel Corporation Device [8086:4dc8] +-1f.4 Intel Corporation Device [8086:4da3] \-1f.5 Intel Corporation Device [8086:4da4] • Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "*superiotool <https://www.coreboot.org/Superiotool> -dV*"). Output of superiotool -dV (minus all the probing/failed): Found ITE IT8613E (id=0x8613, rev=0xc) at 0x2e Register dump: idx 20 21 22 23 24 2b val 86 13 0c 40 00 48 def 86 13 05 40 00 48 LDN 0x01 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 01 def 00 03 f8 04 00 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 fa fb fc val 01 0a 30 0a 20 00 80 00 00 00 20 00 f0 00 00 00 def 00 02 90 02 30 09 00 00 00 00 00 NA NA 00 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 00 00 60 00 64 01 02 48 def 01 00 60 00 64 01 02 48 LDN 0x06 (Mouse) idx 30 70 71 f0 val 00 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 2d 60 61 62 63 70 71 72 73 74 b0 b1 b2 b3 b4 b8 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc cd da db e0 e1 e2 e3 e4 ec f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb val 00 f7 80 08 d1 00 41 02 0a 10 0a 00 00 01 00 00 00 00 00 00 00 00 00 00 00 c0 03 01 06 80 48 90 00 00 00 00 00 00 b0 44 00 00 00 00 00 00 00 00 00 00 00 00 0e 00 00 00 00 00 def 00 f3 00 00 00 01 01 00 00 00 00 00 00 00 20 38 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA 00 00 0e 00 00 00 00 00 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 06 • Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "*flashrom <http://flashrom.org/> -p internal -V*" Direct inspection shows 8-pin 16MB w25q128jv, however, flashrom doesn't seem to include that in the list of Winbond chips it probes for. dmidecode says it's an 8MB ROM, so not sure why the discrepancy • Step 5: URL to the mainboard specifications page (optional). Topton (branded) https://www.aliexpress.com/item/1005004374464011.html Can't find official specs, but there's a pho • Step 6: Any other relevant information you can provide. There's a photo of the board on the left of this BIOS update page https://www-changwang-com.translate.goog/down/74.html?_x_tr_sl=zh-CN&_x_tr_… I've been Googling both "Jasperlake coreboot" and "n5105 coreboot". I see there was news of starting to support this back in January 2020 https://www.phoronix.com/news/Coreboot-JSP-TGL-Razer-ICL Looking at some Coreboot commits, I see a "jasperlake-rvp" target was added, so I simply tried it out. It seems to build fine, but with two warnings: ** WARNING ** ADD_FSP_BINARIES isn't selected even though this SoC relies on the FSP. The resulting image won't contain the FSP binaries and will not boot unless they are added later. ** WARNING ** coreboot has been built without an Intel Firmware Descriptor. Never write a complete coreboot.rom without an IFD to your board's flash chip! You can use flashrom's IFD or layout parameters to flash only to the BIOS region. The first warning seems to suggest I can't ignore is (as it won't boot). I thus went looking for an FSP bin for this chip. Unfortunately it doesn't seem to be in the official Intel Github repo, and there's an unanswered issue there looking for it https://github.com/intel/FSP/issues/74 I hope that provides the necessary info to make a start! Thanks Marcos

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