coreboot

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39654 discussions

New on blogs.coreboot.org: Embracing a New Era: 9elements and AMD Collaborate to Bring Open-Source Firmware to 4th Gen EPYC Server Systems
by blogs.coreboot.org 18 Apr '23

18 Apr '23

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Re: Supermicro X11SSH-LN4F PCI-e bifurcation?
by Kyösti Mälkki 16 Apr '23

16 Apr '23

On Sun, Apr 16, 2023 at 12:33 AM Tomas <tomas(a)fritiofson.se> wrote: > > Hi > Thank you. > I flashed the OEM firmware back on to the chip, tried the bifurcation card with two NVMe drives, and dumped lspci oputput to file. > There is a setting in the UEFI setup where you can set PCI-e SLOT5 Bifurcation to "Auto" or x4x4. > Hi, please reply to mailing list too. I left out the complete lspci you sent, but attached here is the relevant section. It is PCI 0:1.1 and 0:1.2 that require different configuration from what stock coreboot now does. I think the patch I sent previously has a fair likelihood of working. Auto-detection or a choice in menuconfig is something that can come later. Kyösti

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SMSC- EMC2300 driver
by Ahmet Fenerci 14 Apr '23

14 Apr '23

Hello, We have an Intel (Denverton, cpu:C3758) Harcuvar custom board. We use SMSC-EMC2300 fan controller in the board. It works on i2c bus but driver not available. Is it possible to add SMSC-EMC2300 driver in coreboot? Kind regards, Ahmet FENERCİ

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X200 GPU slowdown that needs to be cured by S3
by Artem Mazurov 13 Apr '23

13 Apr '23

Hello. Whenever I try to run any program that uses 3D acceleration (like glmark2), after a short while performance drops significantly (From 14 FPS running terrain benchmark to 3 FPS) and persists until S3. What could be the problem and how can I troubleshoot this? Since S3 fixes it, maybe it's something with coreboot? cbmem.log attached.

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Supermicro X11SSH-LN4F PCI-e bifurcation?
by Tomas 13 Apr '23

13 Apr '23

Hi, I installed Coreboot with SeaBIOS on a Supermicro X11SSH-LN4F. The stock BIOS can read two NVMe drives in a Dual m.2 splitter card inserted in the middle slot 5 on the motherboard. But coreboot can not. In the coreboot nconfig menu there is no setting that will enable bifurcation of the x8 slot to x4x4. Is this something that is configurable in any way? /Tomas

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request for support new hardware from coreboot
by Artem 12 Apr '23

12 Apr '23

Hello Im Artem from Khadas https://www.khadas.com/ We developing new product our hardware based on: Alder Lake ULT 12th Gen Intel Core i7-1280P We have plans to use coreboot as alternative bootloader for our new product We need some information about: 1) coreboot possibilities for current hardware 2) estimated time to create some initial workable prototype 3) what information we need provide for your side at this moment we use BIOS from AMI: Vendor: Amerian Megatrends Core Verion: 5.27 Compiancy: UEFI 2.8; PI 1.7 etc... About us We are Shenzhen Wesion Technology Co., Ltd is the company that owns the brand "Khadas", our company was founded on 5 November 2014. We focus on developing, manufacturing and marketing single board computers (SBCs) ... more info https://www.khadas.com/about Best regards Artem

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proposal for cross compilation: add Rust support
by ron minnich 07 Apr '23

07 Apr '23

https://review.coreboot.org/c/coreboot/+/74124 First step, which I almost certainly did incorrectly, is to add Rust toolchain support to the Makefile. Next, adding a rust payload was suggested. I'll look into that, probably rewriting linuxcheck in rust (since I'm the only user anyway :-)

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[coreboot - Bug #121] T520: Hangs in OS
by Evgeny Zinoviev 07 Apr '23

07 Apr '23

Issue #121 has been updated by Evgeny Zinoviev. On my x230 with gentoo, with recent kernel the situation has worsened significally. If on 5.x kernels it worked somewhat stable (I had crashes maybe once in a month or so and maybe it wasn't even coreboot related), now I after upgrade to 6.1.12-gentoo and it freezes like twice a day. This might be completely bug-121-unrelated, but limiting max cstate to c3 seems to fix the issue, so I decided to report here anyway... can anybody confirm the same? I mean that the newer kernel == more freezes/crashes ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1466 * Author: Julz Buckton * Status: New * Priority: Normal * Start date: 2017-06-09 ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[RFC] vboot recovery reason clearing
by Michał Żygowski 06 Apr '23

06 Apr '23

Hi coreboot folks, I have recently stumbled upon an issue that non-ChromeOS platforms, once entered into recovery mode, cannot leave this state, despite the RW partition being updated with correctly signed firmware copy. I.e. imagine situation where RW A (and B) is not valid, vboot logic causes to boot into recovery. Flash is updated with valid RW A (and B) but the vboot logic does not try to verify the RW partition, instead is stuck in recovery mode due to VBOOT NVRAM content. For ChromeOS platform the recovery reason is cleared in vb2api_kernel_phase2 but vb2api_kernel_phase2 is probably not used anywhere except depthcharge (or whatever is loading the ChromeOS kernel). So non-ChromeOS platform using vboot have no option to get out of recovery. Unless I am missing something, then please correct me. My suggestion would be to add vb2_clear_recovery to vb2api exposed to the coreboot and let the platform code decide when the recovery request should be cleared. Also coreboot can attempt to verify RW partition despite recovery reason, but it would probably be inefficient and lead to situations where recovery mode should be entered, but wasn't entered. Dear ChromeOS firmware experts, your opinion is highly appreciated. Best regards, -- Michał Żygowski Firmware Engineer GPG: 6B5BA214D21FCEB2 https://3mdeb.com | @3mdeb_com

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Coffeelake Graphics Problem
by cagatay bagci 05 Apr '23

05 Apr '23

Hello all,I have a custom CFL board. I used Tianocore UEFI payload. It boots without problem on console and I can enter BIOS menu. I put appropriate vbt.bin file and added that path to config file, so VBT exists. However, I cannot get display output. I inspected debug log and it says "graphics hand-off block not found" in one line. I understand that FSP does not build "gEfiGraphicsInfoHobGuid". Do you have an idea why FSP does not produce that HOB? In addition to that, by using FSP debug binary, I can see that FSP does not even enter PeiGraphicsEntryPoint. It somehow quits after "SerialIoInit() Start" and notifys Post PCI Enumeration. Thanks,

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