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17 participants
39654 discussions

Coffeelake Reset S5 Problem
by cagatay bagci 29 Mar '23

29 Mar '23

Hello all,We have a custom CFL board that resembles CFL RVP-11. I compiled the code and flashed it and it started booting without problem. However after global reset, it stucks at S5 and S5 signal asserts low. Because of that, microcontroller does not power up the system. What might be the problem? Log is ending here: [INFO ] Done allocating resources.[0m[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 75 ms[0m[DEBUG] GLOBAL RESET![0m[INFO ] global_reset() called![0m[DEBUG] HECI: Global Reset(Type:1) Command Thanks,

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[coreboot - Bug #121] T520: Hangs in OS
by Anastasios Koutian 29 Mar '23

29 Mar '23

Issue #121 has been updated by Anastasios Koutian. File defconfig added Andrey A. wrote in #note-70: > T420 and IVB cpu here again. > After 9 months with intel_idle.max_cstate=4 (and last kernel and coreboot) I get a full stable system without a freeze. I have a similar setup: Mainboard: T420 CPU: i7-3940XM RAM: Corsair Vengeance 16 GB DDR3 1600 MHz (CMSX16GX3M2A1600C10) iGPU: Intel HD Graphics 4000 dGPU: NVIDIA Quadro NVS 4200M Coreboot version is CBET4000 4.16-1069-gf4905da14c using MrChromebox's old "corebootpayload" branch as payload (which is now deprecated, I think). Intel ME was stripped. Coreboot config is attached. With intel_idle.max_cstate=2 the system is stable. Any higher value results in the freezes as described above (sometimes with the glitch on the left side of the screen, sometimes without). It's weird how intel_idle.max_cstate=4 doesn't work for me. If anyone is still looking into this, I would be happy to help. ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1455 * Author: Julz Buckton * Status: New * Priority: Normal * Start date: 2017-06-09 ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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GSoC 2023 participation
by Shivani Joshi 29 Mar '23

29 Mar '23

Hello, I am Shivani Joshi, a third year computer engineering undergraduate. I am looking forward to participating in the GSOC 2023 program for coreboot. The following projects interested me while going through the list of projects. 1. Provide toolchain binaries 2. Fully support building coreboot with the Clang compiler I have already completed building coreboot on my linux system. As mentioned on the contributing page, I have begun solving the scan-build issues. I have experience with programming arm processors and have an affinity towards low-level programming. I am attaching the serial output on the terminal after building the code along with this email. Regards, Shivani

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Please Unsub me from this feed
by ivankalashnikov＠outlook.com 29 Mar '23

29 Mar '23

-- Sincerely, Ivan Kalashnikov

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GSoC 2023-Provide Toolchain Binaries
by Komal S 29 Mar '23

29 Mar '23

Hello All! This is Komal Sambhus from Mumbai, India. I had earlier expressed my interest for the project 'Provide Toolchain Binaries'. It would be great to get in touch with the mentors for this project to proceed further. Thanking You in Advance, Regards, Komal

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[GSOC 2023] Libpayload based memtest payload
by Joursoir 24 Mar '23

24 Mar '23

Hello everyone, I'm interested in participating in GSoC 2023. I would like to take part in the development of the coreboot, moreover I already have a bunch of commits in the flashrom. I find the "Libpayload based memtest payload" project interesting and have a few questions about it. 1) This project was added a few years ago, also coreboot payload of memtest based on memtest from 2019 (however, in 2022 memtest86+ v6 is released). So, maybe something has changed since that time and not reflected in the docs? I found such ticket: https://ticket.coreboot.org/issues/184 2) Do I understand correctly, that this payload should be memtest-fork with a difference that will be built on libpayload and a design that will allow multiple architectures to be added? 3) There are no mentors at the moment :( I would appreciate any feedback. -- Joursoir

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Introduction
by Yuchen He 22 Mar '23

22 Mar '23

Greetings, My name is Yuchen He, I'm a first year computer science student from Germany and I'm interested in the coreboot project as well as participating in Google Summer of Code. I'm interested in computer hardware and architecture and also low level programming, so I hope to learn more about these through a GSoC project. Some interesting projects I came across are: - Work on tools to extract register information from datasheets. (For Intel datasheets for instance) - A tool to generate vboot maps automatically - Add additional unit tests - Complete serialICE integration into coreboot but I wouldn't mind doing any other project. Best regards! :)

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Hardware Compatibility Help
by parakawa＠tutanota.com 22 Mar '23

22 Mar '23

Hi, Hope you are having a wonderful day. Kindly requesting if the following two laptops can install coreboot? Lenovo Yoga 13 Intel Core i7 - Model Number 20175 & Lenovo Thinkpad X1 Carbon Intel Corei7 Please let me know if any further information is required. Regards, Parakawa

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GSoC contributor
by fikretgaripay 21 Mar '23

21 Mar '23

Dear coreboot community, My name is Fikret Garipay, and I am a final year Electrical Electronics Engineering student. I want to participate in this year's GSoC and contribute to coreboot. I have experience working with C, QEMU, Linux, git, and Bash. In addition, I have hands-on hardware experience using popular tools like flashrom. I own a coreboot-compatible g41m-es2l motherboard-based desktop and a Dell Optiplex 7010, which I have used to gain practical knowledge of coreboot. I have been developing my skills in UEFI and coreboot through the Open Security Training 2 courses. As a result, I feel prepared to contribute to the following projects: - Fully support building coreboot with the Clang compiler - Port payloads to ARM, AArch64, or RISC-V - Libpayload-based memtest payload - Fix POST code handling I have attached a log file containing the serial output of the tutorial as evidence of my work. Furthermore, I have pushed a commit to address a potential memory leak identified by scan-build. I am eager to contribute to the coreboot community and work alongside experienced developers to improve the projects. I am looking forward to receiving feedback, guidance, and mentorship from the community. Thank you for considering my application. I am excited to start contributing and making a positive impact on coreboot and its related projects. Best regards, Fikret Garipay

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4.20 release preparations
by Felix Singer 17 Mar '23

17 Mar '23

Hi everyone, 2 months passed since last release and the 4.20 release is ahead of us. I'm starting with the release preparations on Monday, which means I'm going through the patches on Gerrit (also the merged ones) and see what could add some value to the release and what needs more documentation. Patches, which should be included in the release, are marked with the following hashtag: coreboot_release_4.20 Patches lacking of documentation (no matter if release notes, user or developer documentation), are marked with the following hashtag: coreboot_needs_documentation Hashtags can be added by everyone, but the field for that is a little bit hidden. Once you have a patch open, click on "Show all" in the top left corner and then the hashtag field shows up in the list. Please feel free to add any of these hashtags yourself. In addition to that, add at least me to the reviewer list so that I'm getting notified and aware of it. If you add the hashtag for missing documentation, also add a comment about what exactly is missing. I will try to summarize the status at the end of each week. Felix

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