coreboot

coreboot@coreboot.org

17 participants
39654 discussions

Getting onboard NIC recognized as enoX instead of enpXsX
by Kevin Keijzer 06 Mar '23

06 Mar '23

Hello, I've been trying to figure out how predictable interface naming works, especially the "on-board index number", that the firmware apparently passes(?) I'm currently working on a port for the ASRock B75M-ITX, which has a Realtek NIC as PCI device 03:00.0. The Linux kernel calls this device enp3s0, which makes sense and works fine. However, on my ASUS P8Z77-V and my Lenovo X230, the Intel NIC is called eno0, which makes more sense, because it's "ethernet onboard 0" and not a physical network card stuck in a PCI Express slot. At first I thought that maybe this was an e1000e-specific way of naming interfaces, but at the office I have an old Gigabyte GA-G41M-ES2L-based file server, running coreboot, also with a Realtek NIC, also being PCI device 03:00.0, which is called eno0 by the kernel as well, with enp3s0 as altname. (So it's not that.) I ended up reading about the interface (re)naming process, which seems to be handled by systemd-udevd [1]: --- The following different naming schemes for network interfaces are now supported by udev natively: 1. Names incorporating Firmware/BIOS provided index numbers for on-board devices (example: eno1) 2. Names incorporating Firmware/BIOS provided PCI Express hotplug slot index numbers (example: ens1) 3. Names incorporating physical/geographical location of the connector of the hardware (example: enp2s0) 4. Names incorporating the interfaces's MAC address (example: enx78e7d1ea46da) 5. Classic, unpredictable kernel-native ethX naming (example: eth0) --- It looks like my B75M-ITX currently uses option 3, while I want it to use option 1, like all my other machines do. So according to the documentation, interfaces called enoX or ensX use index numbers provided by the firmware. However, I have no idea how or where this is defined. I would expect something to be in devicetree.cb, but I can't see anything seemingly related anywhere. So my question is: how does coreboot pass "index numbers for on-board devices" to the kernel / udev, and how can I define them properly on boards where this is not working the way it should? [1] https://systemd.io/PREDICTABLE_INTERFACE_NAMES/ -- With kind regards, Kevin Keijzer

3 5

Apply for GSoC
by readlnh 06 Mar '23

06 Mar '23

Dear all, My name is Xu LingXiao, i am a computer engineering student from University of Padua. I am interested in the topic "Port payloads to ARM, AArch64 or RISC-V", especially the RISC-V. The reason i want to attend this project is that i just received a risc-v board VisionFive2 from China(i am a Chinese student who study in Italy now), i want to port coreboot to my board. I plan to add payload to risc-v platform starting from qemu and then the real hardware. Now i have gone through the tourial, and here is serial output results(qemu-x86_64): [NOTE ] coreboot-4.19-701-g65c456227e-dirty Sun Mar 05 17:31:38 UTC 2023 x86_32 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x0. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: mcache @0x00014e00 built for 11 files, used 0x280 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x43f0 in mcache @0x00014e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 4 ms [NOTE ] coreboot-4.19-701-g65c456227e-dirty Sun Mar 05 17:31:38 UTC 2023 x86_32 romstage starting (log level: 7)... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x07fff000 254 entries. [DEBUG] IMD: root @ 0x07ffec00 62 entries. [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/postcar' @0x14e80 size 0x50f0 in mcache @0x00014fcc [DEBUG] Loading module at 0x07fd1000 with entry 0x07fd1031. filesize: 0x4de0 memsize: 0xb0f0 [DEBUG] Processing 180 relocs. Offset value of 0x05fd1000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 4 ms [NOTE ] coreboot-4.19-701-g65c456227e-dirty Sun Mar 05 17:31:38 UTC 2023 x86_32 postcar starting (log level: 7)... [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0x4500 size 0xeaba in mcache @0x07ffea2c [DEBUG] Loading module at 0x07fa3000 with entry 0x07fa3000. filesize: 0x1c420 memsize: 0x2cba8 [DEBUG] Processing 1805 relocs. Offset value of 0x03fa3000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 2 ms [NOTE ] coreboot-4.19-701-g65c456227e-dirty Sun Mar 05 17:31:38 UTC 2023 x86_32 ramstage starting (log level: 7)... [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 0000 enabled [DEBUG] DOMAIN: 0000 scanning... [DEBUG] PCI: pci_scan_bus for bus 00 [DEBUG] PCI: 00:00.0 [8086/1237] enabled [DEBUG] PCI: 00:01.0 [8086/7000] enabled [DEBUG] PCI: 00:01.1 [8086/7010] enabled [DEBUG] PCI: 00:01.3 [8086/7113] enabled [DEBUG] PCI: 00:02.0 [1234/1111] enabled [DEBUG] PCI: 00:03.0 [8086/100e] enabled [DEBUG] PCI: 00:01.0 scanning... [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 0 msecs [DEBUG] PCI: 00:01.3 scanning... [DEBUG] scan_bus: bus PCI: 00:01.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 2 msecs [DEBUG] scan_bus: bus Root Device finished in 2 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 2 / 2 ms [DEBUG] found VGA at PCI: 00:02.0 [DEBUG] Setting up VGA for PCI: 00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] QEMU: e820/res: 0xfd00000000 +0x300000000 [DEBUG] QEMU: e820/ram: 0x00000000 + 0x08000000 [DEBUG] QEMU: reserve ioports 0x0510-0x0511 [firmware-config] [DEBUG] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] [DEBUG] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] [DEBUG] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] [DEBUG] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] update_constraints: DOMAIN: 0000 0d base 00000510 limit 00000511 io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0e base 00005658 limit 00005658 io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0f base 0000ae00 limit 0000ae0f io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 10 base 0000af00 limit 0000af1f io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 11 base 0000afe0 limit 0000afe3 io (fixed) [DEBUG] update_constraints: PCI: 00:01.0 01 base 00000000 limit 00000fff io (fixed) [DEBUG] update_constraints: PCI: 00:01.3 01 base 0000e400 limit 0000e43f io (fixed) [DEBUG] update_constraints: PCI: 00:01.3 02 base 00000f00 limit 00000f0f io (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 1000, Size: 4658, Tag: 100 [INFO ] * Base: 5659, Size: 57a7, Tag: 100 [INFO ] * Base: ae10, Size: f0, Tag: 100 [INFO ] * Base: af20, Size: c0, Tag: 100 [INFO ] * Base: afe4, Size: 341c, Tag: 100 [INFO ] * Base: e440, Size: 1bc0, Tag: 100 [DEBUG] PCI: 00:03.0 14 * [0x1000 - 0x103f] limit: 103f io [DEBUG] PCI: 00:01.1 20 * [0x1040 - 0x104f] limit: 104f io [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff [DEBUG] update_constraints: DOMAIN: 0000 0a base fd00000000 limit ffffffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0b base 00000000 limit 0009ffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0c base 000c0000 limit 07ffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 12 base 000a0000 limit 000bffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 13 base 000c0000 limit 000fffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 02 base fec00000 limit fecfffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 03 base fee00000 limit fee0ffff mem (fixed) [DEBUG] update_constraints: PCI: 00:01.0 02 base ff800000 limit ffffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:01.0 03 base fec00000 limit fec00fff mem (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 8000000, Size: f6c00000, Tag: 200 [INFO ] * Base: fed00000, Size: 100000, Tag: 200 [INFO ] * Base: fee10000, Size: 9f0000, Tag: 200 [INFO ] * Base: 100000000, Size: fc00000000, Tag: 100200 [DEBUG] PCI: 00:02.0 10 * [0x8000000 - 0x8ffffff] limit: 8ffffff prefmem [DEBUG] PCI: 00:03.0 30 * [0x9000000 - 0x903ffff] limit: 903ffff mem [DEBUG] PCI: 00:03.0 10 * [0x9040000 - 0x905ffff] limit: 905ffff mem [DEBUG] PCI: 00:02.0 30 * [0x9060000 - 0x906ffff] limit: 906ffff mem [DEBUG] PCI: 00:02.0 18 * [0x9070000 - 0x9070fff] limit: 9070fff mem [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff done [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === [DEBUG] PCI: 00:01.1 20 <- [0x0000000000001040 - 0x000000000000104f] size 0x00000010 gran 0x04 io [DEBUG] PCI: 00:02.0 10 <- [0x0000000008000000 - 0x0000000008ffffff] size 0x01000000 gran 0x18 prefmem [DEBUG] PCI: 00:02.0 18 <- [0x0000000009070000 - 0x0000000009070fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:02.0 30 <- [0x0000000009060000 - 0x000000000906ffff] size 0x00010000 gran 0x10 romem [DEBUG] PCI: 00:03.0 10 <- [0x0000000009040000 - 0x000000000905ffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:03.0 14 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:03.0 30 <- [0x0000000009000000 - 0x000000000903ffff] size 0x00040000 gran 0x12 romem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 5 / 13 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00.0 cmd <- 00 [DEBUG] PCI: 00:01.0 cmd <- 00 [DEBUG] PCI: 00:01.1 cmd <- 01 [DEBUG] PCI: 00:01.3 cmd <- 00 [DEBUG] PCI: 00:02.0 cmd <- 03 [DEBUG] PCI: 00:03.0 cmd <- 03 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 1 / 1 ms [ERROR] Null dereference at eip: 0x7fb23ca [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] CPU: QEMU Virtual CPU version 2.5+. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor AMD device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #0 initialized [INFO ] bsp_do_flight_plan done after 0 msecs. [DEBUG] CPU_CLUSTER: 0 init finished in 2 msecs [DEBUG] PCI: 00:00.0 init [DEBUG] Assigning IRQ 10 to PCI: 00:01.3 [DEBUG] Assigning IRQ 11 to PCI: 00:03.0 [DEBUG] PCI: 00:00.0 init finished in 1 msecs [DEBUG] PCI: 00:01.0 init [DEBUG] RTC Init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x02 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [DEBUG] PCI: 00:01.0 init finished in 1 msecs [DEBUG] PCI: 00:01.1 init [DEBUG] IDE: Primary IDE interface: on [DEBUG] IDE: Secondary IDE interface: on [DEBUG] IDE: Access to legacy IDE ports: off [DEBUG] PCI: 00:01.1 init finished in 0 msecs [DEBUG] PCI: 00:02.0 init [DEBUG] PCI: 00:02.0 init finished in 3 msecs [DEBUG] PCI: 00:03.0 init [DEBUG] PCI: 00:03.0 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 7 / 4 ms [INFO ] Finalize devices... [INFO ] Devices finalized [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 1 / 0 ms [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. [INFO ] Copying Interrupt Routing Table to 0x07f99000... done. [DEBUG] PIRQ table: 128 bytes. [INFO ] QEMU: firmware config: Found 'etc/table-loader' [DEBUG] QEMU: found ACPI tables in fw_cfg. [INFO ] QEMU: firmware config: Found 'etc/acpi/rsdp' [DEBUG] QEMU: loading "etc/acpi/rsdp" to 0x7f75000 (len 20) [INFO ] QEMU: firmware config: Found 'etc/acpi/tables' [DEBUG] QEMU: loading "etc/acpi/tables" to 0x7f75040 (len 131072) [DEBUG] QEMU: loaded ACPI tables from fw_cfg. [DEBUG] Looking on 0x07f75000 for valid checksum [DEBUG] Checksum 1 passed [DEBUG] Checksum 2 passed all OK [DEBUG] ACPI: * SSDT [DEBUG] Found 1 CPU(s). [DEBUG] ACPI: added table 5/32, length now 56 [DEBUG] ACPI tables: 131136 bytes. [DEBUG] smbios_write_tables: 07f6d000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.19-701-g65c456227e-dirty' [DEBUG] SMBIOS: Unknown CPU or CPU doesn't support Deterministic Cache CPUID leaf [INFO ] DOMAIN: 0000 (QEMU Northbridge i440fx) [INFO ] QEMU: firmware config: Found 'etc/smbios/smbios-tables' [DEBUG] QEMU: found smbios tables in fw_cfg (len 321). [DEBUG] QEMU: coreboot type0 table found at 0x7f6d040. [DEBUG] QEMU: loading smbios tables to 0x7f6d08a [DEBUG] SMBIOS tables: 459 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 57e5 [DEBUG] Writing coreboot table at 0x07f9a000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-0000000007f6cfff: RAM [DEBUG] 4. 0000000007f6d000-0000000007fa2fff: CONFIGURATION TABLES [DEBUG] 5. 0000000007fa3000-0000000007fcffff: RAMSTAGE [DEBUG] 6. 0000000007fd0000-0000000007ffffff: CONFIGURATION TABLES [DEBUG] 7. 00000000fec00000-00000000fec00fff: RESERVED [DEBUG] 8. 00000000ff800000-00000000ffffffff: RESERVED [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [DEBUG] Wrote coreboot table at: 0x07f9a000, 0x2ec bytes, checksum ffee [DEBUG] coreboot table: 772 bytes. [DEBUG] IMD ROOT 0. 0x07fff000 0x00001000 [DEBUG] IMD SMALL 1. 0x07ffe000 0x00001000 [DEBUG] CONSOLE 2. 0x07fde000 0x00020000 [DEBUG] TIME STAMP 3. 0x07fdd000 0x00000910 [DEBUG] AFTER CAR 4. 0x07fd0000 0x0000d000 [DEBUG] RAMSTAGE 5. 0x07fa2000 0x0002e000 [DEBUG] COREBOOT 6. 0x07f9a000 0x00008000 [DEBUG] IRQ TABLE 7. 0x07f99000 0x00001000 [DEBUG] ACPI 8. 0x07f75000 0x00024000

1 0

Re: Deprecation of the Intel Quark SoC
by Łukasz Jeleń 02 Mar '23

02 Mar '23

Hi, My background is low level ARM and I want to get familiar with low level x86. I bought galileo v1 because it is cheap, small and handy x86 board. I have built coreboot code. It does not boot "out of the box". I had to add rmu.bin into coreboot.rom. With this logging on uart works. It seems SD/MMC controller also works. Now I'm struggling with: [INFO ] CBFS: Found 'fspm.bin' @0x31c40 size 0x2f000 in mcache @0x80004f84 [ERROR] CBFS ERROR: 'fspm.bin' allocation failure [EMERG] FSPM not available or failed to load! Regards, Łukasz

4 14

GSoC, QEMU serial ouput
by Karim Taha 02 Mar '23

02 Mar '23

NOTE ] coreboot-4.19-638-gac04c2180c Wed Mar 01 15:01:23 UTC 2023 x86_32 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x0. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: mcache @0x00014e00 built for 11 files, used 0x280 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0x43e8 in mcache @0x00014e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 2 ms [NOTE ] coreboot-4.19-638-gac04c2180c Wed Mar 01 15:01:23 UTC 2023 x86_32 romstage starting (log level: 7)... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x07fff000 254 entries. [DEBUG] IMD: root @ 0x07ffec00 62 entries. [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/postcar' @0x14e40 size 0x50f0 in mcache @0x00014fcc [DEBUG] Loading module at 0x07fd1000 with entry 0x07fd1031. filesize: 0x4de0 memsize: 0xb0f0 [DEBUG] Processing 180 relocs. Offset value of 0x05fd1000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 5 ms [NOTE ] coreboot-4.19-638-gac04c2180c Wed Mar 01 15:01:23 UTC 2023 x86_32 postcar starting (log level: 7)... [DEBUG] FMAP: area COREBOOT found @ 200 (4193792 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0x4500 size 0xeaa5 in mcache @0x07ffea2c [DEBUG] Loading module at 0x07fa3000 with entry 0x07fa3000. filesize: 0x1c3a0 memsize: 0x2cb28 [DEBUG] Processing 1803 relocs. Offset value of 0x03fa3000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 3 ms [NOTE ] coreboot-4.19-638-gac04c2180c Wed Mar 01 15:01:23 UTC 2023 x86_32 ramstage starting (log level: 7)... [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 0000 enabled [DEBUG] DOMAIN: 0000 scanning... [DEBUG] PCI: pci_scan_bus for bus 00 [DEBUG] PCI: 00:00.0 [8086/1237] enabled [DEBUG] PCI: 00:01.0 [8086/7000] enabled [DEBUG] PCI: 00:01.1 [8086/7010] enabled [DEBUG] PCI: 00:01.3 [8086/7113] enabled [DEBUG] PCI: 00:02.0 [1234/1111] enabled [DEBUG] PCI: 00:03.0 [8086/100e] enabled [DEBUG] PCI: 00:01.0 scanning... [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 0 msecs [DEBUG] PCI: 00:01.3 scanning... [DEBUG] scan_bus: bus PCI: 00:01.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 3 msecs [DEBUG] scan_bus: bus Root Device finished in 3 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 2 ms [DEBUG] found VGA at PCI: 00:02.0 [DEBUG] Setting up VGA for PCI: 00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [INFO ] QEMU: firmware config interface detected [INFO ] Firmware config version id: 3 [INFO ] QEMU: firmware config: Found 'etc/e820' [DEBUG] QEMU: e820/res: 0xfd00000000 +0x300000000 [DEBUG] QEMU: e820/ram: 0x00000000 + 0x08000000 [DEBUG] QEMU: reserve ioports 0x0510-0x0511 [firmware-config] [DEBUG] QEMU: reserve ioports 0x5658-0x5658 [vmware-port] [DEBUG] QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug] [DEBUG] QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug] [DEBUG] QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0] [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] update_constraints: DOMAIN: 0000 0d base 00000510 limit 00000511 io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0e base 00005658 limit 00005658 io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0f base 0000ae00 limit 0000ae0f io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 10 base 0000af00 limit 0000af1f io (fixed) [DEBUG] update_constraints: DOMAIN: 0000 11 base 0000afe0 limit 0000afe3 io (fixed) [DEBUG] update_constraints: PCI: 00:01.0 01 base 00000000 limit 00000fff io (fixed) [DEBUG] update_constraints: PCI: 00:01.3 01 base 0000e400 limit 0000e43f io (fixed) [DEBUG] update_constraints: PCI: 00:01.3 02 base 00000f00 limit 00000f0f io (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 1000, Size: 4658, Tag: 100 [INFO ] * Base: 5659, Size: 57a7, Tag: 100 [INFO ] * Base: ae10, Size: f0, Tag: 100 [INFO ] * Base: af20, Size: c0, Tag: 100 [INFO ] * Base: afe4, Size: 341c, Tag: 100 [INFO ] * Base: e440, Size: 1bc0, Tag: 100 [DEBUG] PCI: 00:03.0 14 * [0x1000 - 0x103f] limit: 103f io [DEBUG] PCI: 00:01.1 20 * [0x1040 - 0x104f] limit: 104f io [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff [DEBUG] update_constraints: DOMAIN: 0000 0a base fd00000000 limit ffffffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0b base 00000000 limit 0009ffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 0c base 000c0000 limit 07ffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 12 base 000a0000 limit 000bffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 13 base 000c0000 limit 000fffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 02 base fec00000 limit fecfffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 03 base fee00000 limit fee0ffff mem (fixed) [DEBUG] update_constraints: PCI: 00:01.0 02 base ff800000 limit ffffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:01.0 03 base fec00000 limit fec00fff mem (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 8000000, Size: f6c00000, Tag: 200 [INFO ] * Base: fed00000, Size: 100000, Tag: 200 [INFO ] * Base: fee10000, Size: 9f0000, Tag: 200 [INFO ] * Base: 100000000, Size: fc00000000, Tag: 100200 [DEBUG] PCI: 00:02.0 10 * [0x8000000 - 0x8ffffff] limit: 8ffffff prefmem [DEBUG] PCI: 00:03.0 30 * [0x9000000 - 0x903ffff] limit: 903ffff mem [DEBUG] PCI: 00:03.0 10 * [0x9040000 - 0x905ffff] limit: 905ffff mem [DEBUG] PCI: 00:02.0 30 * [0x9060000 - 0x906ffff] limit: 906ffff mem [DEBUG] PCI: 00:02.0 18 * [0x9070000 - 0x9070fff] limit: 9070fff mem [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffff done [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === [DEBUG] PCI: 00:01.1 20 <- [0x0000000000001040 - 0x000000000000104f] size 0x00000010 gran 0x04 io [DEBUG] PCI: 00:02.0 10 <- [0x0000000008000000 - 0x0000000008ffffff] size 0x01000000 gran 0x18 prefmem [DEBUG] PCI: 00:02.0 18 <- [0x0000000009070000 - 0x0000000009070fff] size 0x00001000 gran 0x0c mem [DEBUG] PCI: 00:02.0 30 <- [0x0000000009060000 - 0x000000000906ffff] size 0x00010000 gran 0x10 romem [DEBUG] PCI: 00:03.0 10 <- [0x0000000009040000 - 0x000000000905ffff] size 0x00020000 gran 0x11 mem [DEBUG] PCI: 00:03.0 14 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:03.0 30 <- [0x0000000009000000 - 0x000000000903ffff] size 0x00040000 gran 0x12 romem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 6 / 16 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00.0 cmd <- 00 [DEBUG] PCI: 00:01.0 cmd <- 00 [DEBUG] PCI: 00:01.1 cmd <- 01 [DEBUG] PCI: 00:01.3 cmd <- 00 [DEBUG] PCI: 00:02.0 cmd <- 03 [DEBUG] PCI: 00:03.0 cmd <- 03 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 2 / 1 ms [ERROR] Null dereference at eip: 0x7fb23aa [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [INFO ] CPU: QEMU Virtual CPU version 2.5+. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor AMD device 60fb1 [DEBUG] CPU: family 0f, model 6b, stepping 01 [INFO ] CPU #0 initialized [INFO ] bsp_do_flight_plan done after 0 msecs. [DEBUG] CPU_CLUSTER: 0 init finished in 2 msecs [DEBUG] PCI: 00:00.0 init [DEBUG] Assigning IRQ 10 to PCI: 00:01.3 [DEBUG] Assigning IRQ 11 to PCI: 00:03.0 [DEBUG] PCI: 00:00.0 init finished in 1 msecs [DEBUG] PCI: 00:01.0 init [DEBUG] RTC Init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x02 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [DEBUG] PCI: 00:01.0 init finished in 1 msecs [DEBUG] PCI: 00:01.1 init [DEBUG] IDE: Primary IDE interface: on [DEBUG] IDE: Secondary IDE interface: on [DEBUG] IDE: Access to legacy IDE ports: off [DEBUG] PCI: 00:01.1 init finished in 0 msecs [DEBUG] PCI: 00:02.0 init [DEBUG] PCI: 00:02.0 init finished in 3 msecs [DEBUG] PCI: 00:03.0 init [DEBUG] PCI: 00:03.0 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 7 / 4 ms [INFO ] Finalize devices... [INFO ] Devices finalized [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. [INFO ] Copying Interrupt Routing Table to 0x07f99000... done. [DEBUG] PIRQ table: 128 bytes. [INFO ] QEMU: firmware config: Found 'etc/table-loader' [DEBUG] QEMU: found ACPI tables in fw_cfg. [INFO ] QEMU: firmware config: Found 'etc/acpi/rsdp' [DEBUG] QEMU: loading "etc/acpi/rsdp" to 0x7f75000 (len 20) [INFO ] QEMU: firmware config: Found 'etc/acpi/tables' [DEBUG] QEMU: loading "etc/acpi/tables" to 0x7f75040 (len 131072) [DEBUG] QEMU: loaded ACPI tables from fw_cfg. [DEBUG] Looking on 0x07f75000 for valid checksum [DEBUG] Checksum 1 passed [DEBUG] Checksum 2 passed all OK [DEBUG] ACPI: * SSDT [DEBUG] Found 1 CPU(s). [DEBUG] ACPI: added table 5/32, length now 56 [DEBUG] ACPI tables: 131136 bytes. [DEBUG] smbios_write_tables: 07f6d000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.19-638-gac04c2180c' [DEBUG] SMBIOS: Unknown CPU or CPU doesn't support Deterministic Cache CPUID leaf [INFO ] DOMAIN: 0000 (QEMU Northbridge i440fx) [INFO ] QEMU: firmware config: Found 'etc/smbios/smbios-tables' [DEBUG] QEMU: found smbios tables in fw_cfg (len 321). [DEBUG] QEMU: coreboot type0 table found at 0x7f6d040. [DEBUG] QEMU: loading smbios tables to 0x7f6d084 [DEBUG] SMBIOS tables: 453 bytes. coreinfo 0.1 CPU Information ────────────────────────────────────────────────────────────────────────────── Vendor: AMD Processor: QEMU Virtual CPU version 2.5+ Family: F Model: 6B Stepping: 1 Brand: 0 CPU Speed: 2355 MHz Features: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflsh mmx fxsr sse sse2 AMD Extended Flags: fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat lahf/sahf svm xsr lm [A: CPU Info] [B: PCI] [C: NVRAM] [D: RAM Dump] F1: System F2: Firmware 03/02/2023 - 01:32:29

1 0

GSoC
by Karim Taha 02 Mar '23

02 Mar '23

Hello all. I'm Karim Taha, my nickname on the irc channel is Kimo. I'm a senior computer engineering student at Cairo University. I'm interested in the "Fully support building coreboot with the Clang compiler" project. I was able to build and test the project with the default options listed in the document tutorial, and currently I'm working on one issue of the small project section.

1 0

Unable to get S3 resume to work on new port
by Kevin Keijzer 01 Mar '23

01 Mar '23

Hello, I'm working on a port for a new board; the ASRock B75M-ITX. A friend of mine did the initial porting [1] based on the existing B75 Pro3-M and autoport. I then took over the board as I intend to build an HTPC around it. Everything works fine, with the exception of resuming from S3. The board goes to sleep fine, but when I resume it, I'm greeted with the payload. (As this board does not have a serial port, I don't have an easy way to get logs, but everything looks like it just does a cold boot because DRAM is reset.) Then I found out that on the ASRock B75 Pro3-M port, which has been in coreboot since 2017, S3 resume also does not work [2]. It is suggested there to find the proper DRAM_RESET_GATE_GPIO, so I tried that. I've compiled and flashed roms with DRAM_RESET_GATE_GPIO set in Kconfig from 0 to 75, but in all cases the board just reboots instead of resumes. So I'm not too sure what to try next. Does anyone have any suggestions? [1] https://review.coreboot.org/c/coreboot/+/73097 [2] https://review.coreboot.org/c/coreboot/+/20227 -- With kind regards, Kevin Keijzer

2 3

ProTip: buy a 5.25" fan controller while you still can
by Mike Banon 01 Mar '23

01 Mar '23

Dear friends, Unfortunately the 5.25" DVD/BluRay drives are less popular nowadays and many companies stopped making the PC cases with 5.25" slots - to make room for some stupid RGB lighting? - not realizing that a lot of people have been using these 5.25" slots for alternative purposes! In example, to host 1) a hot swap dual HDD bay with a built-in RAID controller; or 2) a fan controller - with either a sensor LCD screen or the rotary knobs to control the fan speeds of each channel and even monitor the temperatures of its own thermal sensors. As a result of reduced "with-5.25"" PC cases availability, many 5.25" fan controllers have been discontinued already - in favor of those "soulless" black boxes without any physical controls, that usually can be controlled only with some Windows crapware. Yes, for some of them (i.e. "Corsair Commander Pro") Linux support has been reverse-engineered - however it's not always as refined & feature-complete, obviously still doesn't work in the alternative OSes like Kolibri, occupies an extra USB port for control data exchange, and anyways - having to use a console to adjust the fans is a huge extra hassle compared to an instant physical access. So, especially considering that a coreboot+SeaBIOS do not provide a built-in GUI for the fan speeds setup (+ even if existed, you'd need to reboot your PC to access it) - a 5.25" fan controller is really a must have! And, considering that the Chinese ALSEYE/STW controllers from AliExpress seem to have a higher failure rate (IMHO based on reviews) - it may be a good idea to get the more reliable branded ones while their supplies last. One thing to consider: if it has to be a VFD display, the VFDs have a longer lifespan if they are green - https://en.wikipedia.org/wiki/Vacuum_fluorescent_display Please share your opinion about the fan controllers. Maybe you are already using one? Myself, I'm happy with 'GELID SpeedTouch 6 FC-LC-01' (6 channels & sensor display) in HAF XB EVO case - which simultaneously hosts two AMD no-PSP coreboot motherboards - A88XM-E and AM1I-A - thanks to some modding. Old photos here - https://www.reddit.com/r/coreboot/comments/jn8is5/corebooted_2in1_amd_pc_as… - since that the construction has been improved thanks to a Silverstone Nitrogon NT06-PRO, an unique horizontal cooler which allows to place a fan beneath the heatsink, making it much easier to use its heatsink as a support structure for a "second floor" with AM1I-A. Also, I was lucky enough to get 'Akasa FC.Trio' (3 channels & LCD & rotary knobs) for my new Chieftec Pro Cube CI-02B-OP mATX case - which I got to build the A88XM-E coreboot test stand with an instant access to a BIOS chip. Btw this CI-02B-OP case is still widely available, has a horizontal motherboard placement (so less stress from a heavy RX590 - the last AMD GPU without a built-in PSP), both 5.25" and 3.5" bays (I used a 3.5" bay for two 2.5" HDDs with a hot swap), and an unique fold-open construction for a super convenient access to the internals. The only downside which I've encountered - is a bit tight cable routing of a large PSU; but, if your PSU has the detachable cables (which could be connected one-by-one after the PSU installation), this is much easier to manage. Please share your experiences ;-) -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

1 0

disable efficient-cores or performance-cores in Intel 12th gen processors
by baptx 27 Feb '23

27 Feb '23

Hello, For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cor…), is it supported by coreboot or Dasharo? Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfo…), is it supported also? If some of these disabling option are not available, is there any plan to support them and is there a workaround currently? Thanks.

1 0

Participation in GSoC '23
by Komal S 27 Feb '23

27 Feb '23

Hello All! This is Komal Sambhus here, a second year student from Mumbai, India. I am interested in participating in GSoC 2023 and working for coreboot. While going through the ideas list, the following projects interested me: -Provide Toolchain binaries -Fix POST code handling I have already built coreboot on my Ubuntu 20.04 system and have taken up this issue from the scanbuild index as mentioned in the Projects page. https://coreboot.org/scan-build/ASROCK_G41M_VS3_R2_0-scanbuild/ Are there any tasks relating to these ideas that I must complete or any additional skills that I must acquire before the application process begins? I have worked with embedded systems such as the BeagleBone Black, but am new to coreboot. Thanking You in advance, Komal

1 0

[GSoC] Provide toolchain binaries
by Raysan Alawami 26 Feb '23

26 Feb '23

Hello everyone, I am Raysan Alawami and I am from Saudi Arabia. I plan on participating in GSoC and working on the first idea in the project idea list (see https://doc.coreboot.org/contributing/project_ideas.html#provide-toolchain-…). I have spent quite some time learning and writing small bash scripts, so I think that I can pull this one off. I have a question regarding your target platforms. Do you guys have any specific Linux distros in mind that you want to be supported in the packaging script? At the moment, I intend to support Ubuntu, and Windows or Mac OS for now. I am looking for popular Liunx distros that you guys think should be supported. Also, regarding the testing and verification of the packages, Can I get a tldr on how my scripts will be tested using QEMU/Docker? Or how you guys expect to be able to test them? I want to know a little more about the process so that I can figure out how much of it I can automate using the packaging script, and possibly another script meant for installing the packages on the target platforms for testing the packages. Finally, I have not had the chance to build build coreboot and boot it due to circumstances beyond my control, but I will be sure to post my serial output results before I apply. Thanks, Raysan

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot