coreboot

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39707 discussions

Via EPIA
by Russell Gower 06 May '03

06 May '03

Could someone please point me in the right direction. I need to enable wake on Ring for the onboard serial port and/or AC power recovery on a via epia 5000 mainboard. Thanks Russell

2 1

Delay in copying Linuxbios to ram
by Shubhangi Jadhav 06 May '03

06 May '03

Hi, While trying to boot using linuxbios , I get a message " Copying LinuxBIOS to ram " and then the system pauses for 3-4 secs, before printing the next message - "Jumping to Linuxbios" Could someone tell me what causes this delay, does the process of uncompressing and copying linuxbios to RAM take this long? Any suggestions on how to reduce this delay? Here's the log of the debug messages. ***************log********************************* LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Thu Apr 24 06:42:06 IST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, nsuperio 1 handle_superio Pass 0, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 0, Superio w83627hf handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [8086/7124] PCI: 00:1e.0 [8086/2418] PCI: 00:1f.0 [8086/2410] PCI: 00:1f.1 [8086/2411] PCI: 00:1f.2 [8086/2412] PCI: 00:1f.3 [8086/2413] PCI: 00:1f.5 [8086/2415] PCI: 00:1f.6 [8086/2416] PCI: pci_scan_bus for bus 1 PCI: 01:04.0 [10ec/8139] PCI: 01:05.0 [10ec/8139] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:1e.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:1e.0 24 <- [0xfec00000 - 0xfebfffff] bus 1 prefmem PCI: 00:1e.0 20 <- [0xfeb00000 - 0xfebfffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:04.0 10 <- [0x00001000 - 0x000010ff] io PCI: 01:04.0 14 <- [0xfeb00000 - 0xfeb000ff] mem PCI: 01:05.0 10 <- [0x00001400 - 0x000014ff] io PCI: 01:05.0 14 <- [0xfeb01000 - 0xfeb010ff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:1f.1 20 <- [0x000028e0 - 0x000028ef] io PCI: 00:1f.2 20 <- [0x000028c0 - 0x000028df] io PCI: 00:1f.3 20 <- [0x000028f0 - 0x000028ff] io PCI: 00:1f.5 10 <- [0x00002000 - 0x000020ff] io PCI: 00:1f.5 14 <- [0x00002880 - 0x000028bf] io PCI: 00:1f.6 10 <- [0x00002400 - 0x000024ff] io PCI: 00:1f.6 14 <- [0x00002800 - 0x0000287f] io ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:1e.0 cmd <- 07 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 00:1f.6 cmd <- 01 PCI: 01:04.0 cmd <- 03 PCI: 01:05.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized DRP0 = 0x9 DIMM0 - size = 64M DIMM1 - size = 0M DRP1 = 0x0 DIMM2 - size = 0M totalram: 64M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000678 pf=0x00000001 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Configuring L2 cache...Not 'GenuineIntel' Processor Enable Cache done. Disabling local apic...done. CPU #0 Initialized ioapic southbridge enabled 180 RTC Init Invalid CMOS LB checksum set power on after power fail Please turn on nvram handle_superio start, nsuperio 1 handle_superio Pass 1, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 1, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call init Enabling com device: 03 iobase = 0x02f8 irq=3 handle_superio Pass 1, done #0 handle_superio done handle_superio start, nsuperio 1 handle_superio Pass 2, check #0, s 0000cde0 s->super 0000e138 handle_superio: Pass 2, Superio w83627hf handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 2, done #0 handle_superio done Wrote linuxbios table at: 00000500 - 00000664 checksum 7535 Jumping to linuxbiosmain()... Welcome to start32, the open sourced starter. This space will eventually hold more diagnostic information. January 2000, James Hendricks, Dale Webster, and Ron Minnich. Version 0.1 Regards, Shubhangi

7 15

Missing file (tbootfile.c)
by David Murdie 06 May '03

06 May '03

Just thought I'd mention that one of the files on the developers download page is missing. Its the 'C' code for tbootfile (Second last link on the download page) and the current link refers to it being in /developer/code/tbootfile.c Just thought I'd let you know. I initially tried sending this to webmaster(a)linuxbios.org, but it got bounced so I thought this would be the next port of call. (It probably doesn't need to go to the mailing list) Thanks, -- David Murdie __________________________________________________ Yahoo! Plus For a better Internet experience http://www.yahoo.co.uk/btoffer

1 0

Hammer Documentation is now Available at AMD's website
by ebiederman＠lnxi.com 06 May '03

06 May '03

So far I have just skimmed the Documentation but it appears that AMD has now publicly published everything needed to do Hammer LinuxBIOS port. No great surprise but it is nice to actually see it ! Yeah! The chaos with the Dual Athlons has finally paid off :) Eric

6 10

Where to download the latest LinuxBIOS code
by siva kumar 06 May '03

06 May '03

Hi, I want to download the lates LinuxBIOS code. I am not able to download it from the CVS server. SO is it possible to get the Latest LinuxBIOS source code in the tar format. Thanks, Siva

1 0

Re: Debugging the linuxBIOS code
by Andrew Ip 06 May '03

06 May '03

Deepak, > Thanks. I like this list for it's good responses. > Could you please elaborate on "POST card", what is it exactly ? > You are correct, I do not have a simulator. It is a PCI card which displays the value of port address 80. In LinuxBIOS source, it is not hard to find, eg. intel_chip_post_macro(0x11) It will dump 0x11 to port 80, and POST card will display 11 on its LED. While debugging, you can record the value and search thru the source to see where LinuxBIOS hangs. However, you can't do backtracing with this device. -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. Tel: (852)2542 2046 Fax: (852)2542 2036 For public pgp key, please obtain it from http://www.keyserver.net/en.

3 2

Suitable Dual-x86 motherboard
by asdfas asdfasdf 06 May '03

06 May '03

Hi, I'm looking to buy a dual-processor x86 motherboard for my home PC. I'd like to play with LinuxBIOS on it. Could someone please recommend a suitable motherboard ? Thanks, G _________________________________________________________________ MSN 8 with e-mail virus protection service: 2 months FREE* http://join.msn.com/?page=features/virus

1 0

flash_rom problem
by Serafino Sorrenti 06 May '03

06 May '03

with the commit on serial_video i don't have any problem to make linuxbios.rom but when i probe to run flash_rom linuxbios.rom i have this output root@hashOne:~/freebios/util/flash_and_burn# ./flash_rom ../config/pcchips/linuxbios.rom Calibrating timer since microsleep sucks ... takes a second Setting up microsecond timing loop 574M loops per second OK, calibrated, now do the deed Trying Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Trying At29C040A, 512 KB probe_jedec: id1 0xda, id2 0xb Trying Mx29f002, 256 KB probe_29f002: id1 218, id2 11 Trying SST29EE020A, 256 KB probe_jedec: id1 0xda, id2 0xb Trying SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Trying SST39SF020A, 256 KB probe_39sf020: id1 0xda, id2 0xb Trying SST39VF020, 256 KB probe_39sf020: id1 0xda, id2 0xb Trying W29C011, 128 KB probe_jedec: id1 0xda, id2 0xb Trying W29C020C, 256 KB probe_jedec: id1 0xda, id2 0xb Trying W49F002U, 256 KB probe_49f002: id1 0xda, id2 0xb W49F002U found at physical address: 0xfffc0000 Part is W49F002U root@hashOne:~/freebios/util/flash_and_burn# Tnx Serafino

1 0

EEPROM not found
by Philippe CABANNES 06 May '03

06 May '03

>Yours is VT8233. >I don't know how they are different (couldn't find a datasheet >online), >but just try inserting this line around line 437 of flash_rom.c >(inside enables[] = {...}) and see what happens: > {0x1106, 0x3177, "VT8233", enable_flash_vt8231}, This doesn´t work but my south bridge is a vt8235. I also didn´t find data sheets and i really wonder how to do... -------------------------------------------------- Oreka ! Nous sommes l'internet moins cher ! Surfez 25% moins cher avec http://www.oreka.com

3 3

Re: No keyboard.
by Richard Smith 05 May '03

05 May '03

ron minnich wrote: > > can you run a user-mode program in linux (with serial console of course) > and test the keyboard from that? > > I do that a lot for this type of thing, saves time. Not really sure how thats any faster than just doing it in keyboard.c? I hack in some debug code to linuxbios way faster then writing a user-mode program. Believe it or not I haven't even setup a kernel for this system with serial console enabled. Guess its about time to do that. -- Richard A. Smith rsmith(a)bitworks.com

2 1

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