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PLCC paged flash?
by Andre Dias 09 May '03

09 May '03

Hello Folks, Is there any PLCC fkash chip that has paged memory like DOC, so we could use in the new motherboards?

4 3

Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by Richard Smith 09 May '03

09 May '03

>>RAMTEST is usually good enough to catch errors so bad you >>can't get past the BIOS without fixing them. > > Agreed. But the part in question has proved in the past to be unusually > difficult (for me anyway) to get working. For this case I think memtest86 > is appropriate. I guess I don't understand how memtest86 is going to load and run if he can't sucessfully jump to a loaded elf image. -- Richard A. Smith rsmith(a)bitworks.com -- Richard A. Smith rsmith(a)bitworks.com

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problem on boot
by Serafino Sorrenti 09 May '03

09 May '03

After make the linuxbios rom i have this problem, the machine is look on boot, and this is the log of the serial port. PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum ba14 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784576 N I am now initializing the ide system init_drive sectors_per_track = [0], num_heads = [0],num_cylinders=[0], num_sectors = [0] CHS mode... Boot: (hd0,0)/kernel The machine is stalled with this messagges. Tnx Serafino

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problem on boot
by Serafino Sorrenti 09 May '03

09 May '03

this is the full log of minicom Welcome to minicom 2.00.0 OPTIONS: History Buffer, F-key Macros, Search History Buffer, I18n Compiled on Apr 30 2003, 17:04:09. Press CTRL-A Z for help on special keys 0 LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 starting... Copying LinuxBIOS to ram. LinuxBIOS-1.0.0 Tue Aug 13 16:28:27 HKT 2002 booting... Finding PCI configuration type. PCI: Using configuration type 1 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 0, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 0, Superio SiS 950 handle_superio port 0x0, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 0, done #0 handle_superio done Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1039/0730] PCI: 00:00.1 [1039/5513] PCI: 00:01.0 [1039/0008] PCI: 00:01.1 [1039/0900] PCI: 00:01.2 [1039/7001] PCI: 00:01.3 [1039/7001] PCI: 00:01.4 [1039/7018] PCI: 00:01.6 [1039/7013] PCI: 00:02.0 [1039/0001] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1039/6300] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done totalram: 1016M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 512MB, type WB Setting variable MTRR 1, base: 512MB, range: 256MB, type WB Setting variable MTRR 2, base: 768MB, range: 128MB, type WB Setting variable MTRR 3, base: 896MB, range: 64MB, type WB Setting variable MTRR 4, base: 960MB, range: 32MB, type WB Setting variable MTRR 5, base: 992MB, range: 16MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x08 Processor Mask : 0x00 Processor Stepping : 0x00 Feature flags : 0x0183f9ff MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ??????io PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ??????prefmem PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ??????mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07 PCI: 00:00.1 cmd <- 01 PCI: 00:01.0 cmd <- 0c PCI: 00:01.1 cmd <- 03 PCI: 00:01.2 cmd <- 02 PCI: 00:01.3 cmd <- 02 PCI: 00:01.4 cmd <- 03 PCI: 00:01.6 cmd <- 01 PCI: 00:02.0 cmd <- 27 PCI: 01:00.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized Enabled in SIS 503 regs 0x40 and 0x45 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 1, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e handle_superio Pass 1, done #0 handle_superio done PCCHIPS M810LMR (and similar)...Entering the initregs process Southbridge fixup done for SIS 503 handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 handle_superio: Pass 2, Superio SiS 950 handle_superio port 0x2e, defaultport 0x2e handle_superio Using port 0x2e Call finishup handle_superio Pass 2, done #0 handle_superio done Copying IRQ routing tables to 0xf0000...done. Wrote linuxbios table at: 00000500 - 0000066c checksum ba14 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: 0x0000000000008789 Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 Jumping to boot code ROM segment 0x0000 length 0x0000 reloc 0x0000 Etherboot 5.0.6 (GPL) ELF for [SIS900] Boot from (N)etwork or from (L)ocal? clocks_per_tick = 784463 N I am now initializing the ide system init_drive sectors_per_track = [0], num_heads = [0],num_cylinders=[0], num_sectors = [0] CHS mode... Boot: (hd0,0)/kernel this is the output of the serial boot n boot. Tnx Serafino

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810E northbridge initialization problem
by Shubhangi Jadhav 09 May '03

09 May '03

Hi, Here's the northdump and the lspci dump for the 810E northbridge. The only difference I see is in the PCISTS (PCI status) register setting (0x06-07h). Does this affect the ram initialization. In raminit.inc I'm setting the value of this register to 0x2080, but cannot see it being reflected in the northdump output. Could this cause problems in ram initialization? Also I have this small program which sets the value of the PCISTS register, however it modified the register value only the first time and never after that. Any pointers on what could be the reason? **************************northdump output :******************************* 00: 86 80 24 71 06 00 80 00 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 24 71 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 0a 38 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 78 18 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 **************************northdump output :******************************* **************************lspci output :************************************* 00:00.0 Host bridge: Intel Corporation 82810E GMCH [Graphics Memory Controller Hub] (rev 03) 00: 86 80 24 71 06 00 80 20 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 24 71 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 0a 38 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 78 18 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 **************************lspci output :************************************* Regards, Shubhangi

2 2

jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by Deepak Kotian 09 May '03

09 May '03

Hi, after putting some debug statements, it seems the LinuxBIOS resets after the jmp instruction is boot.c ( " jmp *%%eax\n\t" in jmp_to_elf_entry) fails. I am using ETHERBOOT payload with IDE support. Is it because the ram initialization is not proper or something, has anyone experienced this kind of problem. Any pointers, why it should fail over here. Here is the extract of the log ... ********* calling elf load... New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 (cleaned up) New segment addr 0x94000 size 0x8128 offset 0x60 filesize 0x38d4 Loading Segment: addr: 0x0000000000094000 memsz: 0x0000000000008128 filesz: 0x00 000000000038d4 Clearing Segment: addr: 0x00000000000978d4 memsz: 0x0000000000004854 Jumping to boot code at 0x94000 LinuxBIOS-1.0.0 Thu May 1 04:29:36 IST 2003 starting... Ram1 ********* Regards Deepak

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Re: jmp INSTRUCTION IN boot.c fails and resets again , what could be the reason.
by dkotian3＠vsnl.net 09 May '03

09 May '03

I have enabled RAMTEST(ramtest.inc) in the LinuxBIOS, it seems to be running at a very slow pace.Hope it finishes off by today. *****Extract***** dump northbridge: 00: 86 80 24 71 06 00 80 00 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 00 24 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 28 53 09 3c 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 eb fb 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 Done. Testing SDRAM : 80000a00-ffff0f30 SDRAM fill: 887e0000 *****Extract***** The number(887?????) increments at a very slow pace and has been more than an hour now. Moreover, I have 64MB ram, does the above range of test look OK. If has basically happened after changing some parameter in the North Bridge. I have run ramtest before as well without the changes. ****Extract Before ***** Testing SDRAM : 00000000-0009ffff SDRAM fill: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff SDRAM verify: 000000000001000000020000000300000004000000050000000600000007000000080000000900000009ffff Done. ****Extract Before ***** But in this case also, it used to reset... I hope, this what is expected in the Successful Output of Ramtest. Any pointers on this one. Regards Deepak

3 3

Status freebios2...
by ebiederman＠lnxi.com 09 May '03

09 May '03

I am busily working on getting the switching from fallback to normal mode working in LinuxBIOS. To that end I have just implemented and committed structure and typedef support in LinuxBIOS. I realized the other day that to remove assembly code I would need to be able to call rdmsr && wrmsr from code compiled with romcc. rdmsr returns 2 values so I needed structure support. And typedef support was simple to implement and so I fixed it while I was in there. Hopefully I can now make some more progress. Eric

1 0

Re: Flashing Bios Success...
by Nathanael Noblet 08 May '03

08 May '03

On Wednesday, May 7, 2003, at 03:06 PM, ron minnich wrote: > what is your southbridge part? can you look at the part directly? So I have the datasheet for the 5595 now (found using google so not sure whether I should send it to you) um either way to enable flash they talk about using the "address and data port, i.e. Port 70h and 71h, respectively. The access control with which the three portions of registers can be appropriately addressed are stored in PCI-ISA: 45h[3] (EXTEND_EN bit) and PCI-ISA: 45h[1](APCREG_EN bit)." but in the sis530 docs I get this for registers 70h: "Register 70h to register 76h define the attribute of the Shadow RAM from 640 KBytes to 1 MBytes. All of the registers 70h to 75h are defined as below, and each register defines the corresponding memory segment's attribute which are listed in the following table. REGISTER DEFINED RANGE REGISTER DEFINED RANGE Register 70h bits 7:5 0C0000h-0C3FFFh Register 73h bits 7:5 0D8000h-0DBFFFh" so I'm not sure how to set that in the 5595..? There must be some way through the pci bridge I think, but don't really know what I'm doing... so some pointers (or even pointers to some docs on how things work) would be great. Register 45h (on the 5595) controls the flash writability. But on the sis530 45h is "IDE Secondary Channel/Master Drive Data Active Time Control" so again it is a matter of knowing how to communicate with the 5595 instead of the main chipset. Now this is all great and what not, but I'm confused. We're having problems detecting the flash, not writing to it. So I'm not sure how this will help. As well in the flash_rom sources the enable_sis is never called. In going over the sources to devbios and the flash_rom, I realize that I don't know anything much about the pci/isa bridges and such... So basically I'm wondering what the next step is. 1) Does the write enable bit help with detecting? 2) Where do I get docs about how the pci & isa communication happens? 2a) do I need those docs? that's about it... -- Nathanael Noblet Gnat Solutions 4604 Monterey Ave NW Calgary, AB T3B 5K4 T/F 403.288.5360 C 403.809.5368 http://www.gnat.ca/

3 4

Re: My Linux bios FAQ/HOWTO preAlpha
by Richard Smith 08 May '03

08 May '03

McMechan, James W CIV wrote: >>yes, somebody had it and was going to fill it out with more info >>but I have not heard from them. >> >>I'll try to get it to you today. > > That would be me. I was still going over the faq. > Alas I am slow... > The source to the FAQ appears to be the web page's html. Ok.. Well let me know when are ready to add in my stuff. I've added a few more items since my last post. On a sidenote... I've learned that OpenOffice 1.1beta can do DocBook stuff. I'd like to move my text document over to something like that so that you can autogenerate various formats. I pulled down OO1.1b but so far haven't been able to get the DocBook stuff enabled. (You have to go edit some XML config files and I don't seem to have done it correctly). As soon as I can get that setup I'll port my stuff over and attempt to do someting better with the format. And generate it into html,pdf,text, etc. Until then I'm not worrying about formatting. -- Richard A. Smith rsmith(a)bitworks.com

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