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39779 discussions

Re: Fixes for Tyan s2880
by YhLu 30 Jul '03

30 Jul '03

Ron. Changes in raminit.c add fill_last function. So remove following error while kernel booting: " Scanning NUMA topology in Northbridge 24 Node 0 MemBase 0000000000000000 Limit 000000007fffffff Node 1 MemBase 0000000080000000 Limit 00000000f0000000 Node map not sorted 80000000,0 No NUMA configuration found Faking a node at 0000000000000000-00000000f0000000 Bootmem setup node 0 0000000000000000-00000000f0000000 " To: " Scanning NUMA topology in Northbridge 24 Node 0 MemBase 0000000000000000 Limit 000000007fffffff Node 1 MemBase 0000000080000000 Limit 00000000f0000000 Using node hash shift of 24 Bootmem setup node 0 0000000000000000-000000007fffffff Bootmem setup node 1 0000000080000000-00000000f0000000 " Is the raminit.c taken care by ERIC? Is he planning to add 4G support in that? Regards Yinghai Lu

4 7

step 4 in L440GX(HOWTO)
by ylhuang-kimo 30 Jul '03

30 Jul '03

After I do make, I got lot of files and I do make phlash but there is a message on the screen: No rule to make target `vmlinux.bin.gz.block', needed by `phlash'. How can I solve this problem?

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What bootloader is used?
by John Praveen 29 Jul '03

29 Jul '03

I suppose that linuxbiosmain.c is the program that loads the kernel. Is any bootloader used when booting linux from Flash memory into SDRAM? --------------------------------- Do you Yahoo!? Yahoo! SiteBuilder - Free, easy-to-use web site design software

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Re: EPIA-ME6000
by Brian G. Rhodes 29 Jul '03

29 Jul '03

That looks like an EPIA M-10000 compatable board to me. btw, about flash parts, you might more easily find the sst29f040 parts. also macronix makes compatable parts. You're lucky it's not a vt82c686b south as linuxbios does not work very well with that chipset. Brian G Rhodes bgr(a)linespeed.net brhodes(a)visualcircuits.com +1 612-741-1191 On Wed, 30 Jul 2003, Leon Woestenberg wrote: > Hello, > > > That board has a VIA vt82c686b south on it? I built linuxbios for a > > similar VIA board (endat) with an 8601 north and vt82c686b south. That > > > Whoops, the heatsinked chip doesn't have the vt82c686 designator, instead > it reads CLE266. You might be right in me setting up the wrong chip there. > > Let me just list the chips I can find on the board, just to make sure that > this > EPIA-EM6000 is like the M9000 board, before we head of in a wrong > direction. > > VT1211 > VT1622 > VT6103 > VT6307S > VT8235 > CLE266 (under the heatsink, next to the processor) > > Regards, > > Leon. >

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size of linuxbios
by paul 29 Jul '03

29 Jul '03

Hi How big is linuxbios? will 256K byte of flash do? I only have a flash burner that will burn 512k byte. I need to know before I download the source. Thanks

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Above 4G RAM
by YhLu 28 Jul '03

28 Jul '03

Eric, I have tried following memconfig on Tyan S2880. It seems ok. 4*1G DDR in CPU0 Memory slots. 2*256M DDR in CPU1 Memory slots. The MB can boot into the end. (Till end). If I use all 1G DDR, It can download the image but can not execute it and reboot again. Any advise? Regards Yinghai Lu

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Re: K8 + 2.4.21 + Tyan S2880
by YhLu 28 Jul '03

28 Jul '03

Eric, My boss has said that I can release the source code to you. Please find out the patch I made. Make the diff to today's tree. I didn't test RON new script and still use the old scripts tools. I strip out the LSI scsi support, because I don't know if there is any license problem, and I have referred to their documents and may need put their FW in the ROM. It's greater you add ops->enable function that make it easy to handle special device. To some device if it is not gotten magic code, it will not get the resource allocate to it. Before that I have to do it in init function and re-allocate the resource to it again. Please refer to my old amd8131_ioapic.c in southbridge/amd8111. Also you init the io_base, upper16 reg, otherwise the device in PCIX will not got io port allocated to them, and will not work. I have tested Stefan's the code about coherent_ht.c, and add some hardcode to it. coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one. coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones. raminit.c and raminit.1.c are till the hardcode one, and I have tried to use the configurable one, but auto.c can not be compiled, it is too big and used up REG? The old one has been renamed to raminit.o.c. To start other cpus, in auto.c We must enable apic and make sure all apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu function. Again, thank you all to answer my questions to help Tyan s2880 work with LinuxBIOS. Regards Yinghai Lu

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static initialization
by Greg Watson 28 Jul '03

28 Jul '03

Stefan, I've added the ability to name parts. This means that you can do the following: cpu k8 "cpu0" register "south" = "&sb0" register "east" = "&cpu1" end cpu k8 "cpu1" register "south" = ... register "east" = ... end southbridge <device>/<vendor> "sb0" end In the k8 directory you will need to add 'config chip.h' to Config.lb, then create a chip.h that contains something like: #ifndef _CPU_K8 #define _CPU_K8 extern struct chip_control cpu_k8_control; struct cpu_k8_config { struct chip *south; struct chip *east; <any other stuff> }; #endif /* _CPU_K8 */ Then add an object that contains the code that deals with 'cpu_k8_control' (see superio/NSC/pc97307/superio.c for an example). Hopefully this will allow you to deal with the hyperchannel setup stuff. Things that still need to be done/other changes: 1. The above scheme assumes that all cpu's actually exist, which may not be the case. Only the first cpu can be relied on to exist. So we need to think about the best way to indicate that subsequent cpu's are optional. One way might be to add the keyword 'optional' to the definition. e.g. cpu k8 "cpu1" optional register "south" = ... register "east" = ... end We could add an extra pass to the chip_configure() routine called CHIP_PASS_PROBE that is called for all devices that are marked optional. It would then be up to the individual device to check for its existence. This could set a flag that means the enable() entry point is called on subsequent passes for the device. One problem with this approach is that you've already set the 'south' field to point at cpu1. If cpu1 doesn't exist then the probe code would need to set this field to 0. Let me know what you think. 2. Ron is testing replacing: cpu p5 end cpu p6 end cpu k7 end cpu k8 end with just 'cpu k8 end', then using the 'dir' command in the k8 Config.lb file to include support for k7, p6, p5. This will hopefully prevent spurious devices from being included in the static tree. 3. You now must declare: extern struct chip_control part_vendor_device_control; in the part specific chip.h file. Cheers, Greg

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Epia-M
by Stefan Reinauer 28 Jul '03

28 Jul '03

* Thomas Wehrspann <thomas(a)wehrspann.de> [030727 20:10]: > is seems that the support for the ecs k7sem got broken. > When i use the current CVS copiling is no problem, but when i boot > linuxbios stops before the mtrr stuff with "Enabling cache...". I have a similar problem with the EPIA-M (latest CVS): Initializing PCI devices... PCI devices initialized totalram: 127M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC [hang] Is this due to the 128MB stick I am using? It seems to get recognized though. Stefan

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Mini-ITX
by John Hearns 28 Jul '03

28 Jul '03

I've been off the linuxbios list for some time. I see there are a few threads on mini-ITX. Can I ask for some pointers to ROM images for EPIA-800 and M10000 Nehemiah boards (I've just got one on order) I see the ones on cwlinux.com - which specific boards are these for? Thanks!

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