coreboot

coreboot@coreboot.org

6 participants
39707 discussions

Start a nNew thread

See you later...
by ebiederman＠lnxi.com 21 Jul '03

21 Jul '03

I will be at the Ottowa Linux Symposium or travelling to and from there for the rest of the week. Eric

1 0

Re: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Eric, In the auto.c, if I enable : sdram_initialize(&cpu1), the linuxbios need another 20k. What happened? Only add one line and the same function has been called ??? Regards Yinghai Lu -----邮件原件----- 发件人: YhLu 发送时间: 2003年7月21日 14:58 收件人: 'ron minnich' 抄送: ebiederman(a)lnxi.com; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: K8 + 2.4.21 + Tyan S2880 Ron, Before fallback is 64k, I make normal image into (512-64)k, and fallback image into 64k, and then cat them into one 512k. Actually the normal is quite loose with a lot of zeros, and the payload is about 20k. So I need to change to Config in the mainboard dir to make sure normal image has 512-96k. or that's to say change several 65536 to 96*1024?? It that right? Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年7月21日 14:49 收件人: YhLu 抄送: ebiederman(a)lnxi.com; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: 答复: K8 + 2.4.21 + Tyan S2880 On Mon, 21 Jul 2003, YhLu wrote: > So fallback image will be 96K? that's how I'm doing it. With a 1 Mbyte flash I don't worry much. ron

2 1

Re: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Eric, I can build the linuxbios. But it is too large and it is around 60k, and tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum is above 65k.So I can not build the images. The Ram conf costs 20k ??? Any advise. Regards Yinghai Lu -----邮件原件----- 发件人: YhLu 发送时间: 2003年7月21日 10:31 收件人: 'ebiederman(a)lnxi.com' 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: K8 + 2.4.21 + Tyan S2880 Eric, Thanks info about ROMCC option about -mcpu=k8. I will try and make the RAM can be configurable. My CPU is C0, In Opteron We may need to manipulate the MSR to enable the apic. Regards Yinghai Lu YhLu <YhLu(a)tyan.com> writes: > Eric, > > My boss has said that I can release the source code to you. > > Please find out the patch I made. Make the diff to today's tree. > > I didn't test RON new script and still use the old scripts tools. > > I strip out the LSI scsi support, because I don't know if there is any > license problem, and I have referred to their documents and may need put > their FW in the ROM. Ah, an interesting problem. > It's greater you add ops->enable function that make it easy to handle > special device. To some device if it is not gotten magic code, it will not > get the resource allocate to it. Before that I have to do it in init > function and re-allocate the resource to it again. Welcome. > Please refer to my old amd8131_ioapic.c in southbridge/amd8111. > Also you init the io_base, upper16 reg, otherwise the device in PCIX > will not got io port allocated to them, and will not work. Sorry I don't quite parse that sentence. > I have tested Stefan's the code about coherent_ht.c, and add some hardcode > to it. > coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one. > coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones. Interesting looking at this code are you working with C0 stepping Opterons? I have the stock B3 and am having fun getting the memory resets in all of the proper places. > raminit.c and raminit.1.c are till the hardcode one, and I have tried to use > the configurable one, but auto.c can not be compiled, it is too big and used > up REG? Looking. It is your romcc options. By default romcc will not use mmx or sse registers unless you tell it that you have them. I have been doing this with -mcpu=k8. The register pressure is much less when you have 24 registers to work with instead of just 8. > The old one has been renamed to raminit.o.c. > > To start other cpus, in auto.c We must enable apic and make sure all > apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu > function. Yep, an interesting way of doing it. > Again, thank you all to answer my questions to help Tyan s2880 work with > LinuxBIOS. Ron, Stefan. Could one of you help with merging Yinghai's code? I might have time, but I don't think I will manage it before I leave for OLS on Tuesday. Eric

3 5

Re: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Ron, Before fallback is 64k, I make normal image into (512-64)k, and fallback image into 64k, and then cat them into one 512k. Actually the normal is quite loose with a lot of zeros, and the payload is about 20k. So I need to change to Config in the mainboard dir to make sure normal image has 512-96k. or that's to say change several 65536 to 96*1024?? It that right? Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年7月21日 14:49 收件人: YhLu 抄送: ebiederman(a)lnxi.com; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: 答复: K8 + 2.4.21 + Tyan S2880 On Mon, 21 Jul 2003, YhLu wrote: > So fallback image will be 96K? that's how I'm doing it. With a 1 Mbyte flash I don't worry much. ron

1 0

答复: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Ron, So fallback image will be 96K? Regards Yinghai Lu -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年7月21日 14:45 收件人: YhLu 抄送: ebiederman(a)lnxi.com; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: K8 + 2.4.21 + Tyan S2880 On Mon, 21 Jul 2003, YhLu wrote: > I can build the linuxbios. But it is too large and it is around 60k, and > tg3.zelf is about 22k, and tg3--ide_disk.zelf is about 24k, then the sum is > above 65k.So I can not build the images. I now routinely set my linuxbios size for 64K with payload size of 32k. romcc is WONDERFUL but it does grow things a bit. ron

2 1

silly ld question
by ron minnich 21 Jul '03

21 Jul '03

anybody know why ld would give you something like this: bash-2.05b$ readelf -l linuxbios Elf file type is EXEC (Executable file) Entry point 0xffff0004 There are 3 program headers, starting at offset 52 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0xffff0000 0xffff0000 0x117d0 0x117d0 RWE 0x1000 LOAD 0x012fd8 0xffffffd8 0xffffffd8 0x00028 0x00028 RWE 0x1000 LOAD 0x013ff0 0xfffffff0 0xfffffff0 0x00000 0x00000 RW 0x1000 Section to Segment mapping: Segment Sections... 00 .rom .payload .reset .id 01 .reset .id 02 bash-2.05b$ emacs ldoptions note that section 00 and section 01 have got the .reset and .id sections. This is misdirecting objcopy to do the wrong thing. What could cause ld to put duplicate section names in two different segments? What's odder: the ldcscripts that produce this file, and the right file: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0xffff0000 0xffff0000 0x10000 0x10000 RWE 0x1000 LOAD 0x011ff0 0xfffffff0 0xfffffff0 0x00000 0x00000 RW 0x1000 Section to Segment mapping: Segment Sections... 00 .rom .payload .reset .id 01 are IDENTICAL. So I guess it's something in how things are compiled? I am stumped at present. ron

1 1

Re: K8 + 2.4.21 + Tyan S2880
by YhLu 21 Jul '03

21 Jul '03

Eric, Thanks info about ROMCC option about -mcpu=k8. I will try and make the RAM can be configurable. My CPU is C0, In Opteron We may need to manipulate the MSR to enable the apic. Regards Yinghai Lu YhLu <YhLu(a)tyan.com> writes: > Eric, > > My boss has said that I can release the source code to you. > > Please find out the patch I made. Make the diff to today's tree. > > I didn't test RON new script and still use the old scripts tools. > > I strip out the LSI scsi support, because I don't know if there is any > license problem, and I have referred to their documents and may need put > their FW in the ROM. Ah, an interesting problem. > It's greater you add ops->enable function that make it easy to handle > special device. To some device if it is not gotten magic code, it will not > get the resource allocate to it. Before that I have to do it in init > function and re-allocate the resource to it again. Welcome. > Please refer to my old amd8131_ioapic.c in southbridge/amd8111. > Also you init the io_base, upper16 reg, otherwise the device in PCIX > will not got io port allocated to them, and will not work. Sorry I don't quite parse that sentence. > I have tested Stefan's the code about coherent_ht.c, and add some hardcode > to it. > coherent_ht.o.c is the original one. Coherent_ht.1.c is total hardcode one. > coherent_ht.c and coherent_ht.2.c are modified with some hardcode ones. Interesting looking at this code are you working with C0 stepping Opterons? I have the stock B3 and am having fun getting the memory resets in all of the proper places. > raminit.c and raminit.1.c are till the hardcode one, and I have tried to use > the configurable one, but auto.c can not be compiled, it is too big and used > up REG? Looking. It is your romcc options. By default romcc will not use mmx or sse registers unless you tell it that you have them. I have been doing this with -mcpu=k8. The register pressure is much less when you have 24 registers to work with instead of just 8. > The old one has been renamed to raminit.o.c. > > To start other cpus, in auto.c We must enable apic and make sure all > apic_id is right. Please refer to mainboard/tyan/s2880/auto.c boot_cpu > function. Yep, an interesting way of doing it. > Again, thank you all to answer my questions to help Tyan s2880 work with > LinuxBIOS. Ron, Stefan. Could one of you help with merging Yinghai's code? I might have time, but I don't think I will manage it before I leave for OLS on Tuesday. Eric

1 0

EPIA-M, linuxbios + power button
by Dave Ashley 21 Jul '03

21 Jul '03

Under award bios the power button did an instant off. Under linuxbios I have to hold the power button down for 4 seconds to get the power to go off. I vaguely remember reading about controlling the power button, but I can't find it in the docs. Does anyone know how to fix this?

3 3

about linux bios on newer boards...
by Tamer Higazi 21 Jul '03

21 Jul '03

Hi! I'd like to buy a new Computer and i am using Linux continuesly. I have asked myself if a Linuxbios could run on a newer board. Either i am asking myself, if a linuxbios could halt (run down) my linux machine if i push the power switch on my computer as it is allready possible on WinXP. For any help and answer thank you Tamer

1 0

EPIA-M SPD progress
by Dave Ashley 20 Jul '03

20 Jul '03

I used the freebios/util/scanspd code as a starting point and found out the DDR ram is at slot 0x50 and can be accessed through standard SMBus reads at io ports 0x500+. A dump of my working eeprom is this: 128 8 7 12 10 1 64 0 4 117 117 0 128 8 0 1 14 4 12 1 2 32 0 160 117 0 0 80 60 80 45 32 144 144 80 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 Then 0's. These are read using int i; unsigned char val; smbus_wait_until_ready(); for(i=0;i<64;++i) { smbus_read_byte(0x50,i,&val); printf("%d%c",val, (i&15)==15 ? '\n' : ' '); } The southbridge vt8235 code sets 1106:3177 RxD1 + RxD2 in its misc_setup.inc. So standard smbus reads should be available at dram init time. Probe vs SPD discussion: I think the question is which produces a better result, regardless of complexity. Probing seems to have disadvantages in that it can't know how to set timing amounts, signal levels, or clock delays. It would only allow you to figure out the right column bit size I expect. What disadvantages does SPD have other than it is more complex? Wouldn't it let you then be able to correctly use any DDR module you want? -Dave

7 8

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot