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GDT in entry16/32.inc
by Xavier Pegenaute 05 Jun '03

05 Jun '03

Hello, for curiosity is there any specific reason for put values in the first entry of GDT in the file src/cpu/i386/entry[16|32].inc ?. The content of the first entry is: .globl EXT(gdtptr) gdt: EXT(gdtptr): .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ .word 0 ... etc ... Xavi. Regards.

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boot problem with compact flash
by Serafino Sorrenti 04 Jun '03

04 Jun '03

Command? Max cpuid index : 1 Command? Vendor ID : AuthenticAMD Command? Processor Type : 0x00 Command? Processor Family : 0x06 >>>>> >>>>> Too many errors encountered; the rest of the message is ignored: > Processor Model : 0x08 > Processor Mask : 0x00 > Processor Stepping : 0x00 > Feature flags : 0x0183f9ff > > > MTRR check > Fixed MTRRs : Enabled > Variable MTRRs: Enabled > > Disabling local apic...done. > CPU #0 Initialized > Allocating PCI resources... > ASSIGN RESOURCES, bus 0 > PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] mem > PCI: 00:00.1 10 <- [0x00002c90 - 0x00002c93] io > PCI: 00:00.1 14 <- [0x00002ca0 - 0x00002ca3] io > PCI: 00:00.1 18 <- [0x00002cb0 - 0x00002cb3] io > PCI: 00:00.1 1c <- [0x00002cc0 - 0x00002cc3] io > PCI: 00:00.1 20 <- [0x00002c80 - 0x00002c8f] io > PCI: 00:01.1 10 <- [0x00002000 - 0x000020ff] io > PCI: 00:01.1 14 <- [0xfc100000 - 0xfc100fff] mem > PCI: 00:01.2 10 <- [0xfc101000 - 0xfc101fff] mem > PCI: 00:01.3 10 <- [0xfc102000 - 0xfc102fff] mem > PCI: 00:01.4 10 <- [0x00002400 - 0x000024ff] io > PCI: 00:01.4 14 <- [0xfc103000 - 0xfc103fff] mem > PCI: 00:01.6 10 <- [0x00002800 - 0x000028ff] io > PCI: 00:01.6 14 <- [0x00002c00 - 0x00002c7f] io > PCI: 00:02.0 1c <- [0x00001000 - 0x00001fff] bus 1 ÿÿÿÿÿÿio > PCI: 00:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 ÿÿÿÿÿÿprefmem > PCI: 00:02.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 ÿÿÿÿÿÿmem > ASSIGN RESOURCES, bus 1 > PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem > PCI: 01:00.0 14 <- [0xfc000000 - 0xfc01ffff] mem > PCI: 01:00.0 18 <- [0x00001000 - 0x0000107f] io > Allocating VGA resource > done. > Enabling PCI resourcess...PCI: 00:00.0 cmd <- 07 > PCI: 00:00.1 cmd <- 01 > PCI: 00:01.0 cmd <- 0c > PCI: 00:01.1 cmd <- 03 > PCI: 00:01.2 cmd <- 02 > PCI: 00:01.3 cmd <- 02 > PCI: 00:01.4 cmd <- 03 > PCI: 00:01.6 cmd <- 01 > PCI: 00:02.0 cmd <- 27PCI: 01:00.0 cmd <- 03 > done. > Initializing PCI devices... > PCI devices initialized > Enabled in SIS 503 regs 0x40 and 0x45 > handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 > handle_superio Pass 1, check #0, s 0000b040 s->super 0000b318 > handle_superio: Pass 1, Superio SiS 950 > handle_superio port 0x2e, defaultport 0x2e > handle_superio Using port 0x2e > handle_superio Pass 1, done #0 > handle_superio done > PCCHIPS M810LMR (and similar)...Entering the initregs process > Southbridge fixup done for SIS 503 > handle_superio start, s 0000b040 nsuperio 1 s->super 0000b318 > handle_superio Pass 2, check #0, s 0000b040 s->super 0000b318 > handle_superio: Pass 2, Superio SiS 950 > handle_superio port 0x2e, defaultport 0x2e > handle_superio Using port 0x2e > Call finishup > handle_superio Pass 2, done #0 > handle_superio done > Copying IRQ routing tables to 0xf0000...done. > Wrote linuxbios table at: 00000500 - 0000066c checksum bc14 > > Welcome to elfboot, the open sourced starter. > January 2002, Eric Biederman. > Version 1.2 > > 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000ffff > Found ELF candiate at offset 0 > New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 > (cleaned up) New segment addr 0x400000 size 0xcba0 offset 0x60 filesize 0x8789 > Loading Segment: addr: 0x0000000000400000 memsz: 0x000000000000cba0 filesz: > 0x0000000000008789 > Clearing Segment: addr: 0x0000000000408789 memsz: 0x0000000000004417 > Jumping to boot code > ROM segment 0x0000 length 0x0000 reloc 0x0000 > Etherboot 5.0.6 (GPL) ELF for [SIS900] > Boot from (N)etwork or from (L)ocal? clocks_per_tick = 941374 > N > I am now initializing the ide system > init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], > num_sectors = [503808] > LBA mode supported > > Boot: (hd0,0)/kernel > rawread (post_loop) ide_read_sector failed > File not found > Probing...[SIS900]Found SIS900 ROM address 0x0000 > The PCI BIOS has not enabled this device! > Updating PCI command 0003->0007. pci_bus 00 pci_device_fn 09 > Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000 > > sis900_probe: MAC addr 00:0A:E6:4B:4A:AF at ioaddr 0X2000 > sis900_probe: Vendor:0X1039 Device:0X0900 > sis900_probe: No MII transceivers found! > No adapter found > <sleep> > <abort> > Boot from (N)etwork or from (L)ocal? N > I am now initializing the ide system > init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], > num_sectors = [503808] > LBA mode supported > > Boot: (hd0,0)/kernel > File not found > Probing...[SIS900]Found SIS900 ROM address 0x0000 > Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000 > > sis900_probe: MAC addr 00:0A:E6:4B:4A:AF at ioaddr 0X2000 > sis900_probe: Vendor:0X1039 Device:0X0900 > sis900_probe: No MII transceivers found! > No adapter found > <sleep> > <abort> > Boot from (N)etwork or from (L)ocal? N > I am now initializing the ide system > init_drive sectors_per_track = [32], num_heads = [16],num_cylinders=[984], > num_sectors = [503808] > LBA mode supported > > Boot: (hd0,0)/kernel > File not found > Probing...[SIS900]Found SIS900 ROM address 0x0000 > Found SIS 85C503/5513 PCI to ISA bridge ROM address 0x0000 > > sis900_probe: MAC addr 00:0A:E6:4B:4A:AÆ > > > > > > this is the error on boot in my serial console, but in the Compact flash the > file /kernel is here and don't have any problem. > > Tnx Serafino

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Request for Status update of LinuxBios for SC1200 chipset
by Narendra PAtel 04 Jun '03

04 Jun '03

Dear Christer, After going through the mar2002 freebios mailing list I read about your achievement of SC1200 board working with linuxbios!!! As you mentioned in that mail that you had not tested graphics and Audio. Could you please update us with the present status of Linuxbios development for NSC's SCx2xx chipset? Does that final working code or patch being uploaded or can the final working code be available to us for our application which is very similar to Dorado II platform(SC1200 based)? Did you achieved booting WinCe using Linuxbios? Linuxbios homepage has posted one news that Linuxbios can boot windows 2000!!!! but the code is not yet posted. Thanks and regards, Narendra Patel. _________________________________________________________________ Technical writer?. Earn more now! http://server1.msn.co.in/msnleads/tis/index.asp Find out how.

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PS/2 irq problem...[EPIA]
by NEWBELL7＠magicn.com 04 Jun '03

04 Jun '03

Hello!! Have you seen any ps/2 problem on EPIA ? If you have PS/2 mouse & keyboard at same time on EPIA, mouse moving makes problem for ps/2 working. After that , keyboard also didn't work. If you use gpm for mouse, both of mouse & keyboard didn't work. And If you unload gpm, keyboard buffer data while using gpm print on screen suddenly. Do you know this problem? If you have any idea, let me know. please. Thank you. regards, newbie

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Re: Different BOF (LINUXBIOS BOF) (fwd)
by ron minnich 03 Jun '03

03 Jun '03

linuxbios BOF at Usenix. thanks ron ---------- Forwarded message ---------- Date: Tue, 3 Jun 2003 14:42:11 -0700 From: Jennifer Desimone <jdesimone(a)usenix.org> To: ron minnich <rminnich(a)lanl.gov> Subject: Re: Different BOF (LINUXBIOS BOF) >Hello Ron, > >Here is your USENIX '03 BoF confirmation: > >Wednesday, June 11 >Salon K >9:00pm-10:00pm >LinuxBIOS BoF Ron Minnich, Los Alamos National Lab >We can only provide you with an overhead projector and screen. If >you'd like to arrange for additional audio-visual equipment at your >BoF, please contact Al Hymer, Marriott Rivercenter Event >Technology Manager, via email at <al.hymer(a)marriott.com>. Thanks, Jennifer Desimone Conference Assistant USENIX Association 2560 Ninth Street Suite 215 Berkeley, CA 94710 510.528.8649 x30 Fax 510.548.5738 jdesimone(a)usenix.org >On Fri, 30 May 2003, ron minnich wrote: > >> On Fri, 30 May 2003, Jennifer Desimone wrote: >> >> > 1) What day would you like to schedule your BoF? > > >wednesday > >1 hour > >> > 3) What time would you like to begin your BoF? >> > >9pm > >> > 4) What is the title of your BoF? > >LinuxBIOS BOF > >> > 5) What is the name & affiliation of the BoF presenter? >> >> Ron Minnich >> Los Alamos National Lab >> >> > 6) How many people do you think may attend? > > >That's a tough one. It could be anywhere form 5 to 30 > >thanks > >ron --

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Alternatives implementations f LinuxBios
by Xavier Pegenaute 03 Jun '03

03 Jun '03

Hello, i'd like to know where i can find information about alternative implementations of LinuxBios. At the moment i have: - LinuxBios with Standard Flash - LinuxBios with DoC - LinuxBios with CF (i don't have info, yet) - Some other ? Regards. Xavi.

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Does LinuxBios Supports National's SC1200 ?
by Narendra PAtel 03 Jun '03

03 Jun '03

Hello group, Can anybody please tell if the LinuxBios supports the National's SC1200 Chipset? And what if I have load WinCE using LinuxBios? Thanks in Advance! best regards, Narendra Patel _________________________________________________________________ Attention NRIs! Send money to India. http://server1.msn.co.in/msnleads/citibankrca/citibankrca2.asp Do it in a jiffy!

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[9fans] 4-node plan9 cluster (fwd)
by ron minnich 31 May '03

31 May '03

just FYI, linuxbios + plan9 cluster. ron ---------- Forwarded message ---------- Date: Fri, 30 May 2003 13:31:32 -0600 (MDT) From: andrey mirtchovski <mirtchov(a)cpsc.ucalgary.ca> Reply-To: 9fans(a)cse.psu.edu To: 9fans(a)cse.psu.edu Subject: [9fans] 4-node plan9 cluster this is the cluster Ron will show on usenix: http://pages.cpsc.ucalgary.ca/~mirtchov/p9/cluster/ andrey

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[PATCH] XIP for low address (0xf0000) support
by SONE Takeshi 31 May '03

31 May '03

Ron, please apply this patch. It should not break anything, and significantly speeds up booting of certain boards like EPIA. This patch does two things: - Add write-through cache for 0xf0000-0xfffff before uncompressing linuxbios_c, if option XIP_LOW is defined. - Changes existing XIP (execute in place) code to use write-through cache instead of write-protect cache. (as Eric suggested) -- Takeshi Index: earlymtrr.inc =================================================================== RCS file: /cvsroot/freebios/freebios/src/cpu/p6/earlymtrr.inc,v retrieving revision 1.4 diff -u -r1.4 earlymtrr.inc --- earlymtrr.inc 8 Aug 2001 02:45:09 -0000 1.4 +++ earlymtrr.inc 31 May 2003 14:59:56 -0000 @@ -35,6 +35,22 @@ movl $0x06060606, %edx movl $0x06060606, %eax wrmsr + +#ifdef XIP_LOW + /* enable write through cache for 0xf0000-0xfffff*/ + movl $MTRRfix4K_F0000_MSR, %ecx + rdmsr + movl $0x04040404, %edx + movl $0x04040404, %eax + wrmsr + + movl $MTRRfix4K_F8000_MSR, %ecx + rdmsr + movl $0x04040404, %edx + movl $0x04040404, %eax + wrmsr +#endif /* XIP_LOW */ + #endif /* MEMORY_HOLE */ set_var_mtrr: @@ -56,12 +72,12 @@ wrmsr #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE) - /* enable write protect caching so we can do execute in place + /* enable write through caching so we can do execute in place * on the flash rom. */ movl $0x202, %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE | 0x005), %eax + movl $(XIP_ROM_BASE | 0x004), %eax wrmsr movl $0x203, %ecx

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SiS630 Watchdog driver
by Alexander Amelkin 30 May '03

30 May '03

Hello guys! Coming back to the old topic of the SiS630 watchdog driver, I must say that I found a ready one. Available as a patch here: http://www.linuxlabs.com/LinuxBIOS/patches/sis630-wd-2.4.x.patch The driver is kind of 'risky' as it doesn't check for the presence of the SiS630 chipset but, in case if we're cautious, it may be working and useful. It would be nice if someone tested it as I don't have the board right now. With best regards, Alexander mailto:spirit@reactor.ru

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