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p64h2_enable_ioapic
by Andrew Ip 05 Oct '03

05 Oct '03

Hi, In src/southbridge/intel/82870/p64h2_ioapic.c, p64h2_enable_ioapic is hard coded to initialize io apic address numbers 3,4,5,&8. However, I have a custom board which has 3,4,5,8,9 and 10. In order to get it to work, I have to change for(i=0,dev=0;i<4;i++) { to for(i=0,dev=0;i<6;i++) { To fix it properly, I think we have to detect the number of APIC instead of hard code it. Comment? -Andrew -- Andrew Ip Email: aip(a)cwlinux.com Tel: (852) 2542 2046 Fax: (852) 2542 2036 Mobile: (852) 9201 9866 Cwlinux Limited Unit 202B 2/F Lai Cheong Factory Building, 479-479A Castle Peak Road, Lai Chi Kok, Kowloon, Hong Kong. For public pgp key, please obtain it from http://www.keyserver.net/en.

2 1

Re: LinuxBIOS gone?
by ebiederman＠lnxi.com 05 Oct '03

05 Oct '03

<auto92089(a)hushmail.com> writes: > Hey, I found your email on a web page about LinuxBIOS. > > If the LinuxBIOS home page is out of commission more than temporarily, > as it appears to be, do you think you could post the latest stuff you > have somewhere where I could download it? I never got a chance to download > it, and now that I can't have it, I want it more than ever :-/ I seem to be able to find it and the sourceforge site appears to be working as well. If you continue to have problems the LinuxBIOS list is a good place to mention them. > Please do not send it as an attachment to this email address, as I've > got a very small quota of disk space. LinuxBIOS is not dead so you can just go to http://www.linuxbios.org Eric

2 1

slashdot thread on MS and the BIOS and linuxbios
by Steve Gehlbach 05 Oct '03

05 Oct '03

http://slashdot.org/article.pl?sid=03/10/03/2127213&mode=thread&tid=109&tid… Halfway down are some comments titled "Thank goodness for linuxbios". -Steve

5 4

Re: ep405pc
by Greg Watson 04 Oct '03

04 Oct '03

Update on the ep405pc: getting close! Fixed hardwired address and byte ordering issue with the low-level PIC routines. Now I see: LinuxBIOS-1.1.4 Sat Oct 4 16:54:15 MDT 2003 rebooting... Finding PCI configuration type. Enumerating: Winbond W83C553 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1014/0156] enabled PCI: 00:09.0 [10ad/0565] enabled PCI: 00:0e.0 [1045/c861] enabled PCI: pci_scan_bus returning with max=00 done dev_configure: Allocating resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 14 <- [0xfe9ff000 - 0xfebfefff] prefmem PCI: 00:0e.0 10 <- [0xfebff000 - 0xfebfffff] mem ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:00.0 cmd <- 06 PCI: 00:09.0 cmd <- 07 PCI: 00:0e.0 cmd <- 02 done. Initializing devices... Devices initialized Found W83C553F controller Error: Cannot find W83C553F function 1 device No memory size information! Cheers, Greg

1 0

V2 EPIA: success
by ron minnich 03 Oct '03

03 Oct '03

Linux is now up. Tweak this, tweak that in southbridge and at some point it works. Looks like we needed some ISA config to make it go. So V2 is up on the EPIA. Now if we can all come to closure on the config tool we'll be getting there :-) This afternoon I will try to get the memory system to be sane. Wow, this is fun, these little EPIAs are great cluster nodes. Small box, wrapped in steel so I can't break anything, powered by a wall wart. I love 'em. ron

2 3

one other EPIA question
by ron minnich 03 Oct '03

03 Oct '03

is there a register somewhere we can read to figure out FSB clock rate (66 vs 133). This is important for timing. ron

2 1

V2 VIA EPIA -- SPD.
by ron minnich 02 Oct '03

02 Oct '03

OK, the first SPD work is in. Ram size is now set from SPD. The next line of attack are the MA registers. The code is walking a tight line between code space size and register allocation; see northbridge/via/vt8601/raminit.c for some details. These old pentiums are tight on registers! That said, doing this in C is even better than having an ICE. ron

2 2

Re: V2 VIA EPIA
by YhLu 02 Oct '03

02 Oct '03

Any plan on moving other to V2? Intel chipset? Serverworks chipset? Sis chipset? Other?? Regards YH -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年10月2日 16:37 收件人: linuxbios(a)clustermatic.org 主题: V2 VIA EPIA OK, I'm done for a while. This thing is working well enough, I have some other things to do, and I think it is an ok example (criticism is welcome and appreciated, as long as it comes with suggestions for how to improve things). I did put some timing test and control in raminit.c, and it computes what looks like OK timing numbers, but if I use those numbers the machine locks up. You can see the code if interested in CVS. That's what i remember about this north bridge -- it's tricky to get it right. I think we should just leave it at the most conservative timings for now. I would like to know if there are other SPD parameters we ought to try to compute besides MA. Size was an important one to figure out, and it works now, but there are others we might want. Note that right now, due to space limitations, only the first two DRAM slots are getting configured. Please let me know if this is an issue for anyone. ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

V2 VIA EPIA
by ron minnich 02 Oct '03

02 Oct '03

OK, I'm done for a while. This thing is working well enough, I have some other things to do, and I think it is an ok example (criticism is welcome and appreciated, as long as it comes with suggestions for how to improve things). I did put some timing test and control in raminit.c, and it computes what looks like OK timing numbers, but if I use those numbers the machine locks up. You can see the code if interested in CVS. That's what i remember about this north bridge -- it's tricky to get it right. I think we should just leave it at the most conservative timings for now. I would like to know if there are other SPD parameters we ought to try to compute besides MA. Size was an important one to figure out, and it works now, but there are others we might want. Note that right now, due to space limitations, only the first two DRAM slots are getting configured. Please let me know if this is an issue for anyone. ron

1 0

Memory speed
by ron minnich 02 Oct '03

02 Oct '03

Is there a handy-dandy memory timing too out there? I am used to using lmbench but I'd like something a bit smaller and simpler. Thanks ron

1 0

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