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v2 -- status of epia-m (m!!!)
by Niki Waibel 24 Oct '03

24 Oct '03

what is the current dev status of epia-m in v2? niki

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Totally mystified w/ V2
by Dave Ashley 24 Oct '03

24 Oct '03

Well I'm having no luck trying to figure out how to build V2. No doc files, just some ".tex" files which tex doesn't like. Some files that the old configure method doesn't work on: dash% python ../util/config/NLBConfig.py ../targets/via/epia/Config.lb /ram/freebios2 /ram/freebios2/targets/via/epia/Config.lb:5: arch, target, or mainboard must be the first commands, not loadoptions Can someone tell me how to build the epia target in the freebios2 tree? Here's some stuff that should make this thread easier to find building with v2 building with linuxbios version2 building with linuxbios v2 how-to build version2 Thanks-- Dave

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customization
by mannitol 23 Oct '03

23 Oct '03

I have not yet attempted to set up a linux bios. From the guides that I've skimmed through so far I think I shouldn't have too much trouble. I was wondering what kinds of customization options are included. I would like to display a bitmap as the bios loads and hide any messages that would normally be displayed. I know, of course, that this can be done. Unfortunatly I am not much of a programmer. Is there a relatively easy way to do this? Any help would be appreciated.

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AMD64: Something's missing?
by Stefan Reinauer 22 Oct '03

22 Oct '03

Building the Quartet target with latest CVS I get: raminit.c:2378.43: is_cpu_pre_c0 undeclared I'll look into it.. Stefan -- Architecture Team SuSE Linux AG

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RE: AMD64: Something's missing?
by Alan Mimms 22 Oct '03

22 Oct '03

One thing that encryption in the bootstrap CAN do is prevent Trojan attacks against the kernel image. If attackers can't find out what the encryption key is they can't create a substitute Trojan kernel. It plugs a hole. Alan Mimms, Senior Architect F5 Networks, Inc. Spokane Development Center Liberty Lake, Washington v: 509-343-3524 f: 509-343-3501 -----Original Message----- From: SONE Takeshi [mailto:ts1@tsn.or.jp] Sent: Wednesday, October 22, 2003 2:18 AM To: Evan Langlois Cc: linuxbios(a)clustermatic.org Subject: Re: AMD64: Something's missing? On Tue, Oct 21, 2003 at 10:26:01PM +0200, Evan Langlois wrote: > > > EtherBoot can boot lots of things from the network or an IDE hard disk. > > FILO can boot from IDE hard disk, IDE CDROM, floppy, and maybe more? 9load > > I don't know much about except that it is used to load the plan9 kernel. > > I don't know much about FILO. Can anyone comment on its compatibility with > the LILO graphical features (displaying graphical menus/splash screens), and > is there any support available for encrypted filesystems? FILO is not aimed at being compatible with LILO. > Assuming FILO works like LILO, and doesn't know about filesystems, I'm > assuming encryption would be difficult, and it might therefore be best to > chain-load another boot-loader, but I'd want the encryption keys to be in the > ROM to make it as difficult as possible to get to them. FILO has filesystem routines borrowed from GRUB, so it works like GRUB rather than LILO. > Encryption in the BIOS itself may be a positive feature, not just for > corporate users that want to protect their IP, but laptop users and such (in > which case the key would be asked for on boot) that don't want sensitive > information leaking out just because a laptop was stolen. Encryption in boot process doesn't make sense to me. What you want to protect is the data in the storage, not the boot image (kernel). Encryption of the storage is OS's bussiness, and the OS will ask you the password before decrypting any data. -- Takeshi _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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[COMMIT] romcc-0.37
by ebiederman＠lnxi.com 22 Oct '03

22 Oct '03

Ok. Non inline function calls are trickier than I expected. My intuition said I just needed to tweak the generated intermediate code and I could reuse all of my optimizing back end. In almost all cases my back end looks at the code generated declares it spaghetti and refuses to compile it. However I did manage a lot of good general cleanups. I believe I have fix the problem with reading ints instead of bytes from structures. I have optimized the code somewhat so sub word size loads can now be into any of the 8 general purpose registers. I have converted practically all the compile time options into run time switches so the code is a little cleaner and more configurable. Before I return to working on non inlining I need to step back and think some more to see which technique will work best. Either improving my code analysis algorithms, or compiling the functions separately and then inserting calls. There are pluses and minuses to both techniques. Hopefully I will be a little more active now that I have come to a stopping place. Eric

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FW: Forth
by Gregg C Levine 21 Oct '03

21 Oct '03

Hello (again) from Gregg C Levine Folks, take a look at the forwarded message below my signature. It seems to me, that it was spawned from my messages discussing the OpenBIOS kernel. I am inviting advice, and comment. I have responded twice to the person, but so far no replies. ------------------- Gregg C Levine hansolofalcon(a)worldnet.att.net ------------------------------------------------------------ "The Force will be with you...Always." Obi-Wan Kenobi "Use the Force, Luke." Obi-Wan Kenobi (This company dedicates this E-Mail to General Obi-Wan Kenobi ) (This company dedicates this E-Mail to Master Yoda ) -----Original Message----- From: werty(a)swissinfo.org [mailto:werty@swissinfo.org] Sent: Monday, October 20, 2003 5:13 AM To: hansolofalcon(a)worldnet.att.net Subject: Forth Read your post on Forth . Where can i get on mailing list. I want to write a DTC Forth for i386 . It will be fast as it has 3 subroutine levels and lowest level is not Called , but the primatives Do have Returns at end ? ha ha They jmp directly to next primative . Stack must be preserved and restored to exit the prim' . ______________________________________________________________________ _ Dreaming of a Swiss Account? Get it here: http://freemail.swissinfo.org

1 0

V2 EPIA - IDE compat mode, RAM init, and early MTRR
by SONE Takeshi 21 Oct '03

21 Oct '03

Attached patch fixes IDE compatibility mode (so FILO works), and RAM initialization, so the DIMM on the second slot works. SPD is not used by this patch, we have to figure out how to type MA mapping by SPD (see the comment in the code). Maybe I will work on SPD-based RAM timing. earlymtrr.c should go to src/cpu/p6 so the XIP works. The change in src/cpu/p6/mtrr.c just reverse the change made by Eric for K8.. -- Takeshi

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AMD8151
by Stefan Reinauer 21 Oct '03

21 Oct '03

Hi, I still don't get the 8151 to work properly on the solo board. i believe that the link setup looks like: Athlon64 | 8151 | 8111 since athlon64 has only one ht link. my config.lb defines: northbridge amd/amdk8 "mc0" southbridge amd/amd8151 "amd8151" link 0 end southbridge amd/amd8111 "amd8111" link [1|2] end end What is the right way of describing how the 8111 is connected in the config? And I only get hangs at: NB: Function 3 Misc Control.. IF I set amd8111 link to 0 I get a reboot plus hang at PCI: 03:00.2 [ffff/ffff] disabled amd8111_enable dev: PCI: 03:01.0 lpc_dev: PCI: 01:05.0 index: 9 reg: fe9f -> fce PCI: 03:01.0 [ffff/ffff] disabled PCI: 03:05.0 [14e4/1645] enabled Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0-Fallback Mo Okt 20 11:35:43 CEST 2003 rebooting... I also noticed that not all elements in the capability linked list of the 8151 are HT capabilities. The first one on 8151 is an AGP capability element. Maybe this explains why a different ordered probing is needed, does LinuxBIOS correctly skip AGP capability blocks? Stefan -- ARCHITECTURE TEAM SUSE LINUX AG

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cpu/p6/mtrr.c
by SONE Takeshi 21 Oct '03

21 Oct '03

Eric, Is the below change intended? EPIA has problem with current CVS (resets when setting var mtrr), and it worked again when I reversed this change. According to the Intel System Programming Manual for PIII, bits 36-63 are reserved, and apparently C3 doesn't like it to be set. black:~/src/freebios2/src/cpu/p6$ cvs diff -u -r1.4 -r1.5 mtrr.c Index: mtrr.c =================================================================== RCS file: /cvsroot/freebios/freebios2/src/cpu/p6/mtrr.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -r1.4 -r1.5 --- mtrr.c 19 Jul 2003 04:28:21 -0000 1.4 +++ mtrr.c 11 Oct 2003 06:20:17 -0000 1.5 @@ -92,7 +92,7 @@ base.lo = basek << 10; if (sizek < 4*1024*1024) { - mask.hi = 0x0F; + mask.hi = 0x0FF; mask.lo = ~((sizek << 10) -1); } else { -- Takeshi

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