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cleanup: SMBUS_MEM_DEVICE_[START|END]
by Stefan Reinauer 07 Oct '03

07 Oct '03

Hi, the two config variables SMBUS_MEM_DEVICE_START and SMBUS_MEM_DEVICE_END are only used by ./src/sdram/generic_dump_spd.c. Does it make sense to keep those? dump_spd_registers() could use the ram_controller struct to get the values. Then I would remove SMBUS_MEM_DEVICE_[START|END] occurences in the code. Stefan -- Architecture Team SuSE Linux AG

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Re: w49f002u.c ?
by Damien Charlet 07 Oct '03

07 Oct '03

Ok guys, back on my ol' mail after some other work :) Thanx for all your replies so here's where I am now : 1 - The original chip is a sst39 part whereas my savior has a w49 2 - This is the part referenced by IOSS for epia 3 - This chip almost work with my via : I can flash it, read it, boot on it... BUT there are a few bytes which are not flashed well. The wrong bytes always change after reflash. So, I believe the 49 should work with the epia, at the exception of a little something while flashing. Where could I dig more in depth ? Thx, Damien On Mon, 22 Sep 2003 14:16:55 -0600 (MDT) ron minnich <rminnich(a)lanl.gov> wrote: > On Mon, 22 Sep 2003, Damien Charlet wrote: > > > Sorry, this is related to my previous mail "flash_rom and epia 800". > > > > I got a BIOS Savior on my via epia 800. The chip in the RD1-PL is > > (recognized as ?) a w49f002u. Maybe I should check physically which chip > > is on the savior ? > > my turn to be surprised. The EPIA takes a 49F part? Can somebody fill me > in here -- I didn't think it took these. If it does, well, this is very > good news. > > ron -- Damien(.)Charlet(AT pu-pm.univ-fcomte.fr) Doctorant UIN:78754463 Laboratoire d'Informatique de l'Universite de Franche-Comte FRE CNRS 2661 - Centre de Developement du Multimedia de Montbeliard Tel: +33-(0)3.81.99.47.76 damien.charlet(a)pu-pm.univ-fcomte.fr

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re: K8 MTRR reboot on Solo
by YhLu 06 Oct '03

06 Oct '03

I enabled it, and use X86-64 bin to make elf image with mkelfimage 2.5. Please try my zelf instead. Regards YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年10月6日 10:29 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: Re: K8 MTRR reboot on Solo * YhLu <YhLu(a)tyan.com> [031006 18:12]: > There is an X86-64 option in Etherboot config, did you enable it? yes. But I thought it only affects the binary loader. Should I switch it off? Stefan -- Architecture Team SuSE Linux AG

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Re: K8 MTRR reboot on Solo
by YhLu 06 Oct '03

06 Oct '03

There is an X86-64 option in Etherboot config, did you enable it? Regards YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年10月6日 7:38 收件人: linuxbios(a)clustermatic.org 主题: Re: K8 MTRR reboot on Solo * Stefan Reinauer <stepan(a)suse.de> [031006 14:13]: the card is connected with a cross cable to a HDAMA.. etherboot 5.3.1: > [tg3-5701]Ethernet addr: 00:04:76:F3:A9:CE > Tigon3 [partno(3C996B-T) rev 0105 PHY(5701)] (PCI:33MHz:32-bit) > Link is up at 1000 Mbps, full duplex. TX RX flow control > Searching for server (DHCP)... > ..UDP checksum error > .UDP checksum error > .UDP checksum error > ..Me: 192.168.0.20, Server: 192.168.0.23 > Loading 192.168.0.23:legacybios ... > <takes forever> etherboot 5.3.2: Etherboot 5.3.2 (GPL) http://etherboot.org Tagged ELF for [TG3][IDE] Relocating _text from: [000264d0,00058500) to [0fecdfd0,0ff00000) .ÿProbing pci nic...or (Q)uit? [tg3-5701]Ethernet addr: 00:04:76:F3:A9:CE Tigon3 [partno(3C996B-T) rev 0105 PHY(5701)] (PCI:33MHz:32-bit) Link is up at 1000 Mbps, full duplex. TX RX flow control Searching for server (DHCP)... ..transmit timed out tg3_stop_block timed out, ofs=00003c00 enable_bit=00000002 .<abort> etherboot 5.2.2 seems to be the same as 5.2.0 Best regards, Stefan Reinauer -- Architecture Team SuSE Linux AG _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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K8 MTRR reboot on Solo
by Stefan Reinauer 06 Oct '03

06 Oct '03

Hi, I came a bit further with debugging my mysterious reboots after setting up mtrr. This only happens if I build the image on an AMD64 distribution. With an older x86 distribution, the resulting image is operable. Either my romcc changes were somewhat incomplete, or gcc -m32 on Opteron behaves different than gcc on a 32bit machine. Stefan -- Architecture Team SuSE Linux AG

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TUSL2-C 815ep failed
by Yap Ee Huey 06 Oct '03

06 Oct '03

Hi , I have been trying to get linuxbios working on TUSL2-C ( 815ep chipset ) for half a year already. By using the newest patch from heechul, my motherboard still refuse to boot when trying to load the kernel. It should be a RAM init problem although it seems to be working until trying to load the etherboot ide_disk: * Serial Presence Detect (in heechul's patch) doesn't work on TUSL2-C : smbus cannot detect correct value of RAM dimensions. ** There is a continuous beep sound (not stated in award beep codes, like ambulance :) ) if using linuxbios or no bios is inserted. * Must use aflash.exe to flash the bios. /dev/bios and uniflash doesn't work although the flash rom is recognized. Hence, from point 2 and 3 and some comments from uniflash developer, I am suspecting some hardware protection from ASUS which prevent modification in bios by individual. I hope I am wrong and some of you can point that out. I have the matsonic ms7057 (815ep chipset ) linuxbios source from Heechul which should be newer than the one in linuxbios source tree ( this one has RAM dimension auto detect using SPD registers). By using this raminit.inc, three things have to be changed : configure_buffsc (no autodetect) configure_smrcomp (no autodetect) #define SMB_IO_BASE 0x1000 (IO address may vary) It should work on ms7057 and ga-6oxe. Hope this info can help somebody in future. thx. regards, eehuey _________________________________________________________________ Download ringtones, logos and picture messages from MSN Malaysia http://www.msn.com.my/mobile/ringtones/default.asp

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cpuid max index
by Stefan Reinauer 06 Oct '03

06 Oct '03

Hi, cpuid.c prints the following on Athlon64: Max cpuid index : 1 Vendor ID : AuthenticAMD Processor Type : 0x00 Processor Family : 0x0f Processor Model : 0x04 Processor Mask : 0x00 Processor Stepping : 0x08 Feature flags : 0x078bfbff Now, I guess the max cpuid index should be noticably higher, not only 1. cpuid() in cpuid.h looks ok, though..? Best regards, Stefan Reinauer -- Architecture Team SuSE Linux AG

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romcc and EPIA
by SONE Takeshi 06 Oct '03

06 Oct '03

I noticed romcc has support for MMX/SSE registers and epia/Config.lb does not use it. Is there any problem using MMX registers on a C3? I also wonder why -mcpu=p3 is required to enable MMX support of romcc. IIRC, MMX has been supported since Pentium MMX and up, and Pentium III adds SSE. Isn't it better to have options like -mmmx and -msse, instead of -mcpu=<name>. There are too many CPUs. -- Takeshi

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supporting the EPIA-M 10000 VGA [PMX:##]
by gimyung han 06 Oct '03

06 Oct '03

>>David Hendriks has tested and I have committed these new idt.c and >>vgabios.c You mean Now vga for EPIA-10000 is available? Is it possible to use by setting Config file or is there other way? Thanks for your efforts _________________________________________________________________ 고.. 감.. 도.. 사.. 랑.. 만.. 들.. 기.. MSN 러브 http://www.msn.co.kr/love/

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The Great Cheap EPIA contest.
by ron minnich 05 Oct '03

05 Oct '03

OK, I've found this place: http://www.directron.com/minibarebone1.html Here's the question: how cheap can I build an EPIA node? this means case, power supply, epia, etc. Or how cheap can I get a case so I can get boards from Andrew with LinuxBIOS on them :-) ron

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