coreboot

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24 participants
39543 discussions

support for Epia or other Mini-ITX boards
by Michael Fenner 13 Sep '03

13 Sep '03

Hallo, want to set up a machine with LinuxBios - do not know which board to choose - I want to buy a new one and it has to be small. At the moment I have a FV24 with a VIA 1GHz processor. I'm looking into buying an Eipa, Epia-M or Epia-V board. The status page says that only the Eipa is fully supported - but I would prefer an Eipa-M or Eipa-V. Which one would you recommend if I want to install LinuxBios? Or do you have any other sugestions for a Mini-ITX board? Do you have something like a documentation for installing LinuxBios? Thanks for your help, Michael

2 1

EPIA-M 10000 etherboot
by dhroepaem＠freechal.com 13 Sep '03

13 Sep '03

hello~ i have been testing linuxbios with epia-m10000 and rom emulator. i made the romimage from /freebios/src/mainboard/via/epia-m/example.config. when loaded it to rom emulator and reset, hyperterminal said "x-x-f" but when loaded it and reset after loading original epia-m 10000 bios and reset, etherboot worked successfully. following is the config file # # linuxbios config file for: via epia-m mini-itx # target /opt/cwlinux/buildrom/epia-m # via epia mainboard via/epia-m # enable serial console for debugging option serial_console=1 # option serial_post=1 option ttys0_baud=115200 # option ttys0_baud=57600 option default_console_loglevel=9 option debug=1 # use 256kb standard flash as normal bios option ramtest=1 option use_generic_rom=1 option std_flash=1 #option zkernel_start=0xfffc0000 option rom_size=262144 # payload size = 192kb option payload_size=196608 # use elf loader to load etherboot option use_elf_boot=1 # use etherboot as our payload payload /opt/cwlinux/etherboot/src/bin32/via-rhine.ebi # payload /opt/cwlinux/memtest86/memtest plz, give me some hints~ :-) DDR보다 신난다! 온라인으로 즐기는 3D아바타 댄싱 게임 http://showtime2.freechal.com/index.asp

3 2

EPIA-M 10000 etherboot
by dhroepaem＠freechal.com 13 Sep '03

13 Sep '03

thanks, ron now i have four questions. first, i modified the config file. now linuxbios does not run correctly, but it shows more messages. when load the linuxbios directly, the message is ?xxxxxxxfx~ffxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxffxf when load the linuxbios after doing original bios, the message is linuxbios-1.0.0 2003. 09. 09. (ȭ) 16:04:55 kst starting... dump device: 00000000 00: 06 11 23 31 06 00 30 02 00 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 40: 00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50: e0 00 00 02 c0 04 00 00 22 00 01 01 01 01 00 00 60: 00 00 00 00 e4 00 00 2a 00 00 00 00 00 00 00 00 70: 00 48 00 00 01 00 00 00 01 00 00 00 00 00 02 00 80: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00 b0: 00 00 00 00 c0 00 00 00 aa 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 01 00 40 00 00 00 00 00 00 00.............................= 11 f0: 00 00 00 00 00 00 03 13 00 00 00 00 00 00 00 00 .................................... done...... dump device: 00008800...........0001c60 - 00: 06 11 77 31 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00............................ef] ioup) new segment a 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 .......................................... 40: 00 80 00 00 00 00 00 00 0c 20 00 00 04 00 00 00000 - 0x000010ff] io 50: 09 1d 00 00 00 00 00 00 20 00 00 01 00 00 00 00 ................... 60: 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 00.........cmd ................................................. a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00-07- 00000674 ch c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00ader class! pci devices i d0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 data=0009884e firmware t e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00m linux version 2.4.18 (root@epiam) ( f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 done. dump device: 00008900cache... 30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ffios-e820: 00000000000006d4 - 00000000000a0000 (us 40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ffnuxbios_c.o(.te inode-cache hash 50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff un mount-cache hash table entries: 2048 (or 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff <sleep> < re 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ffr-cache hash table entries: 4096 (order: 2, 16384 b 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff checking 'hlt' instruction... ok.:11 done. dump device: 00000000 check 00: 06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 apnp enabled cmd <- 07 tty 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00k or from (l)ocal? cl 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00: 128 slots per queue, batch=320:01.0 1c <- [ 80: 00 61 00 00 00 00 00 00 00 00 00 00 00 00 00 00rt> boot fr vp_ide: not 100% native m 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 probing...[via 86c100]fou a0: 02 c0 20 00 01 02 00 1f 00 00 00 00 00 02 00 00bm-dma at 0x18e0-0x18e7, bios settings: hda:pio, hd b0: 00 00 00 00 c0 00 00 00 aa 00 00 00 00 00 00 00 io address 1400 ethernet addres c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 analyzing media type,this 40: 45 7f f0 00 00 00 00 00 0c 20 00 00 44 00 0b 08 you might want to try agp_tr 50: 81 1d 09 00 00 b0 ac 50 23 00 00 00 00 00 00 00 linespeed=100mbs fullduplex usb.c: new usb bus registered, assign 90: 00 f1 60 88 a0 c0 00 00 00 20 00 00 00 00 00 00 pci: 00:01.0 [1106/b a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0009. (ȭ) 16:04:55 kst starting... b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00.0 [1106/3038] dump device: c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 23 31 06 00 30 02 00 00 00 06 00 00 00 00 d0: 01 05 01 00 00 00 00 00 00 00 00 00 00 00 00 000.3 [1106/3104] 10: 08 00 0 e0: 00 00 00 00 14 08 00 00 00 00 00 00 00 00 00 00 pci: 00:11. f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 0 00 00 00 00 00 40: 0b f2 00 05 18 1c c0 00 a8 a8 a8 20 ff 00 b6 b600 00 00 eaffff 50: 07 07 07 07 0c 03 00 00 a8 a8 a8 a8 00 00 00 00 00: 06 11 77 31 87 00 10 0 60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00io 70: 02 01 00 00 00 00 00 00 82 01 00 00 00 00 00 000 00 00 00 00 00 00 00 00 00 0018c0 - 0x000018df] i 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 0 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00: 00:01.0 cmd <- 07 p 80: 00 d0: 06 00 71 05 00 00 00 00 00 00 00 00 00 00 00 00d <- 01 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 000: 00 f1 60 00 b0 c0 00 00 10 20 00 00 00 00 00 001 f0: 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 00 pci: 00:10.3 cmd <- 02 a0: 0 done.0 00 copying linuxbios to ram. 00 00 00 jumping to linuxbios. pci: 00 linuxbios-1.0.0 2003. 09. 09. (ȭ) 16:04:55 kst booting... 00 00 00 00 00 00 00 00 00 00i: 00:12.0 cmd <- 83 finding pci configuration type. pci: 00:0d.0 [1106/3044] e0: 00 00 00 0 pci: 00:10.0 [1106/3038] 00 00 00 00 pci: 00:10.1 [1106/3038] setting f pci: 00:10.2 [1106/3038] pci: 00:10.3 [1106/3104]0 05 00 00 00 00 00 00 0 pci: 00:11.0 [1106/3177] pci: 00:11.1 [1106/0571] ff ff ff ff ff ff ff ff pci: 00:11.5 [1106/3059] pci: 00:12.0 [1106/3065]or type : 0x00 pci: pci_scan_bus for bus 1f ff ff ff ff ff ff ff ff f pci: pci_scan_bus returning with max=01 initia pci: pci_scan_bus returning with max=01 b0: donef ff allocating pci resources...ff ff ff ff fix d pci: 00:00.0 register 10(00000008), read-only ignoring itenabled pci: 00:00.0 register 10(00000008), read-only ignoring it ff ff ff ff ff ff ff ff ff ff ff ff ff initialized assign resources, bus 0 pci: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff f pci: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmemthbridge fixup cpu #0 in setting pci: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem0 to 0:d.0 112mb, ra pci: 00:0d.0 10 <- [0xfeb00000 - 0xfeb007ff] mem00 00 00 00ng usb pci: 00:0d.0 14 <- [0x00001800 - 0x0000187f] irq 11 to 0:10.0 rom s pci: 00:12.0 10 <- [0x00001400 - 0x000014ff] io 00 pci: 00:12.0 14 <- [0xfeb02000 - 0xfeb020ff] mem 80: 20 84 59 00 f2 70 00 00 01 04 00 00 00 assigned resources, bus 0 done. et enabling pci resourcess...pci: 00:00.0 cmd <- 06 from (n)etwork o 90: 00 f1 pci: 00:01.0 cmd <- 070 00 00 00 00 00 00 pci: 00:0d.0 cmd <- 07 pci: 00:12.0 cmd <- 07 00 00 00 00 00ec done. initializing pci devices... io address 1400 e pci devices initialized3 totalram: 127m c0: 01 0 initializing cpu #000 00 00 00 00 00 0 enabling cache... setting fixed mtrrs(0-88) type: uca type,this will take severa setting fixed mtrrs(0-16) type: wb d0: 01 05 01 00 00 00 00 00 00 0 done fixed mtrrs0090 via lane3): setting variable mtrr 0, base: 0mb, range: 64mb, type wb linespeed=100mbs fulld setting variable mtrr 1, base: 64mb, range: 32mb, type wb00 not enabled thisrtc i setting variable mtrr 5, base: 124mb, range: 2mb, type wb c0: 01 00 02 done variable mtrrs 00 00 00 00 00 00 clear out the extra mtrr's ju call intel_enable_fixed_mtrr() unknown d0: 06 call intel_enable_var_mtrr()0 00 00 00 00 000000us 00 pc leave setup_mtrrs done. max cpuid index : 1 data=0009884ences vendor id : centaurhauls firmwa e0: 00 00 00 00 00 processor type : 0x00 00 00sion 2.4.18 (root@e processor family : 0x06 processor model : 0x08 fixed mtrrs : enabled variable mtrrs: enabled-provided physical r disabling local apic...done. linuxbios-1.0.0 20 cpu #0 initialized:04:55 kst mainboard fixup final mainboard fixup_bus southbridge fixup6/3044]0 setting firewirehm, page 0000000 assigning irq 12 to 0:d.0 pci: 00:10.0 [1106/303 readback = 12 sear setting usb assigning irq 11 to 0:10.0/3038]urning with max=01oc readback = 11 assigning irq 12 to 0:10.100:10.2 [1106/3038] readback = 12 zone(1 assigning irq 10 to 0:10.2 readback = 10 pci: assigning irq 5 to 0:10.3ommand line: conso readback = 5 setting ethernet 00:11.1 [1106/0 assigning irq 11 t calibrating pci: pci_scan_bus returning with max=0 able() - irq_routing_table located at: 0x000090000.2 cmd <- 0107. memor done.i: pc copying irq routing tables to 0xf0000...done. reserved,0:10.3 cmd <- 0 verifing priq routing tables copy at 0xf0000...failed done00:0 allocating pci resourc wrote linuxbios table at: 00000500 - 00000664 checksum 4050 [0xfeb01000 - 0xfeb010ff] mempci: probing pci hardware welcome to elfboot, the open sourced starter. pci: 00:11.1 20 <- [0x0 january 2002, eric biederman.ci: 00:01.0 24 <- [0xfeb00000 version 1.2 ven linux n done.for l enabling pci resource 000000000037e0.0 cmd <- 06ns clearing segment: addr: 0x00000000000977e0 memsz: 0x0000000000003b48 pci: 00: jumping to boot code at 0x9400001 rom segment 0x0000 length 0x0000 reloc 0x9400 pci_scan_ etherboot 5.0.8 (gpl) tagged analyzing media type,this will take several seconds........okbus sp initializing cpu #0verride linespeed=100mbs fullduplex enab searching for server (dhcp)...setting fixed mtrrs(0-88) type ..me: 192.168.1.102, server: 203.252.137.169 vp_ide: ide controller on loading 203.252.137.169:/vmlinuz.epiam ...(elf)... ............................. i think that the 2th message and the 1th message are same but output type(?) is different. (correct? ㅡ.,ㅡ;) i will be waitting for your advices :) second, after loading the linux kernel, the booting stops with a following message. ... linux kernel card services 3.1.22 options: [pci] [cardbus] [pm] usb.c: registered new driver hub uhci.c: usb universal host controller interface driver v1.1 uhci.c: usb uhci at i/o 0x1880, irq 11 usb.c: new usb bus registered, assigned bus number 1 i don't know why the booting stops here. third, what is the post card? post = power on self test? if it does, how can i check the post card? fourth, what does [pmx:##] mean? :) have a nice day~ DDR보다 신난다! 온라인으로 즐기는 3D아바타 댄싱 게임 http://showtime2.freechal.com/index.asp

1 0

nested description of chains
by Stefan Reinauer 12 Sep '03

12 Sep '03

Hi, looking at the big picture again and again, I don't think that nesting hypertransport devices when doing the chain description is a very good idea as it gives us some limitations. * CPUs (North bridges) don't fit in the scenario, since they might be arranged in a circular chain: CPU-3 --- CPU-2 | | | | CPU-0 --- CPU-1 If trying to pack this into the nested description manner as it is now, we can't describe the fact that it's a circular organization: northbridge amd/amdk8 "mc0" pci 0:18.0 [..] northbridge amd/amdk8 "mc1" pci 0:19.0 northbridge amd/amdk8 "mc2" pci 0:1a.0 northbridge amd/amdk8 "mc3" [..] (nesting ad nauseum) end end end northbridge amd/amdk8 "mc3" [..] (nesting ad nauseum) end end * Non-CPU components can be described as long as they are not ring organized, but for Hypertransport devices the description tries to hide the fact that the organization form is a chain. Adding a nested description for components like a superio chip makes perfect sense, since it's unlikely that superio chips are ever cascaded or put into a circular chain. Also, the connection between the I/O hub (southbridge) and the superio can be seen as a peer-to-peer connection rather than a bus that allows arbitrary links between all components. The reason why I am writing this is that currently we have a hardcoded assumption in in LinuxBIOS' coherent hypertransport setup that looks like this: | | [2] [2] CPU-3 [1] --- [1] CPU-2 [0] [0] | | [2] [2] CPU-0 [1] --- [1] CPU-1 [0] [0] | | [x] means that HT link no x is used for a certain link. But this is not the only available organization method for a hypertransport setup. Assumed a CPU HT device looks like this: | [LDT2] ___|__ | | | CPU0 |-- [LDT1] |______| | | [LDT0] A hypertransport setup like this is a little more complex, but still perfectly valid: _______________ | ______ | | | 8111 | | | |______| | | ___|__ | | | | | | | CPU0 |__| | |______| | ______| | | ________________ | | ___|__ ______ | | | | | | 8131 | | | | | CPU1 |--|______| | | | |______| | | |_____| | |_______ | ___|__ | | | | | CPU2 |--[term] | |______| | ________| | | | | [term] | | ___|__ | | | | | | | CPU3 |------------- | |______| |______| I'll look at getting this scenario supported in the coherent_ht setup. But it would be nice to see configurations like this happen without actually touching the code when working a new opteron based port somewhen in future. Comments? Flames? Stefan -- Architecture Team SuSE Linux AG

3 3

extending "buildrom"
by Stefan Reinauer 12 Sep '03

12 Sep '03

Hi, to get used to the config tool, I wrote the attached little patch to change the buildrom command to allow specifying a filename of a rom file that is produced when building LinuxBIOS i.e. buildrom ROM_SIZE "normal" "fallback" changed to: buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" creating a linuxbios.rom file in the build target directory that consists of the 2 concatenated romimages "normal" and "fallback" This way it's now possible to build several roms with "buildrom" that take the specified "romimage"s that were built. This could i.e. be used to build several roms at once i.e. with different payloads in them. Is this ok to check in? -- Architecture Team SuSE Linux AG

2 1

Re: [COMMIT] Infrastructure Updates 4
by YhLu 11 Sep '03

11 Sep '03

It is AMD-8111 LPC, and 0x47 will trigger SWRST. I have checked the schematic that pin is routed to corresponding LDT_RESET. But it's no luck. PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled Bus 1, device 4, function 0: ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 5). -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年9月11日 5:05 收件人: ron minnich 抄送: YhLu; ebiederman(a)lnxi.com; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 * ron minnich <rminnich(a)lanl.gov> [030908 17:03]: > On Mon, 8 Sep 2003, Stefan Reinauer wrote: > > > Did you have a look at the implementation of hard_reset in reset.c? > > void hard_reset(void) > > { > > set_bios_reset(); > > pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); > > } > > the only reset.c I see is in the mainboard-specific code. Nevertheless > this code really should do the find_device thing. I don't think that the wrong device is used though: 01:04.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) PCI: 01:04.0 [1022/7460] enabled Stefan

1 0

Re: [COMMIT] Infrastructure Updates 4
by ebiederman＠lnxi.com 11 Sep '03

11 Sep '03

Stefan Reinauer <stepan(a)suse.de> writes: > * Eric W. Biederman <ebiederman(a)lnxi.com> [030902 19:28]: > > If you want all of your hypertransport devices to be on bus 0, that is > > feasible but it will take a little more work. Right now each > > hypertranport chain get's it's own bus. > > What is missing to achieve this? Just a little code. Merging busses into bus 0 is an interesting logicistics feat, but the current infrastructure will allow it. > Can this cause trouble with current board implementations? Not it is software only. > In the Tyan update code, some hardcoded bus numbers were changed. We should be able to complete remove that. Right now each Hypertransport chains appears to be it's own bus and all of that information is dynamically calculated. The busses that are Hypertranpsort chains are enumerated just like other busses. The way to look at the code is that: - device.c has the logic to enumerate and assign resources to devices and busses. - pci_device.c has the methods for doing that on pci devices. - hypertransport.c has the methods for doing that with hypertranport devices. - northbridge/amd/amdk8/northbridge.c has the drivers for the amdk8 specific northbridge. In short dynamic resource assignment should now be pretty simple and should remove the need for most of the hard codes. I have committed the code not in a final perfect state. But in a state where it works well enough to be useful. And whatever details we encounter are minor things. Passing information to the dynamic device tree from the static device tree is currently a weak area. But we are building one tree from the other so it is just a matter of a small amount of refactoring if we want to do something better. Basically what remains is to dive into the code see what it is doing, and tweak it a little if is not doing quite the right thing. But usually all that needs to happen is to improve a method of a device so that it operates better. Eric

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Re: [COMMIT] Infrastructure Updates 4
by YhLu 11 Sep '03

11 Sep '03

Eric, Without hard_reset, s2885 is ok now. In the k8/cpufixup.c need compare mmio_basek and 0x3f0000 and then assign that to TOM. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 12:44 收件人: ebiederman(a)lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 Eric, If I disable the hard_reset, it can enumerate from link2 to link0. And the 8131 on link2 and 8151 on link0 all show out. Maybe you can add MACRO to control reverse scan for AMKK8 northbridge. ( link2 then link0) But it continues to reboot. Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 19:17:58 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled PCI: 01:04.6 [1022/746e] enabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] enabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 0 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 Hypertransport link capability not foundPCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled Copying LinuxBIOS to ram. -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:48 收件人: ebiederman(a)lnxi.com 抄送: Stefan Reinauer; LinuxBIOS 主题: re: [COMMIT] Infrastructure Updates 4 Eric, In the hypertransport_scan_chain, if the hard_reset is needed, it may produce problem. Hard_reset call 8111 LPC (B1, D4, F0) reg 0x47 to trigger Reset. But it is called before pci_scan_bus. At that time the 8111 LPC is still unkown. Regards YH -----邮件原件----- 发件人: YhLu 发送时间: 2003年9月4日 10:30 收件人: 'ebiederman(a)lnxi.com' 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: [COMMIT] Infrastructure Updates 4 I still have problems for s2885. Amdk8_scan_bus for MC0 only from link0 to link2. link0 is connected to 8151 and link2 is connected to 8131. Then it reboot again and agin. After I reverse the scan from link2 to link0. It can scan out 8131 and 8111 but hung after "HyperT reset needed" is printed. Maybe the reset.c that I move from hdama got some problems. YH. LinuxBIOS-1.1.42.0_Fallback Thu Sep 4 17:07:56 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... dev->links= 3 Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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re: newer solo motherboards
by YhLu 11 Sep '03

11 Sep '03

Stefan, If you set HAVE_HARD_RESET=0 in the Config.lb, does it work? YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2003年9月8日 12:18 收件人: YhLu 抄送: LinuxBIOS 主题: Re: newer solo motherboards * YhLu <YhLu(a)tyan.com> [030908 18:55]: > HyperT reset needed > HyperT reset not needed > > In the scan_hypertranport_chain.c missed one "else" > > YH. ./src/devices/hypertransport.c:hypertransport_scan_chain() should do the right thing, i.e. trigger a reset. And it seems the reset should go to PCIDEV(1,4,0), as on all other hammer boards. But obviously the code does not do a reset, or does it continue at the same PC afterwards? > SMBus controller enabled > Ram1.00 > setting up CPU00 northbridge registers > done. > Ram2.00 How can i verify that the smbus channels LinuxBIOS uses are correct for my board? The old solos only found RAM in the first socket it seems. > Hyper transport scan link: 0 max: 1 > PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 > PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 > HyperT reset needed [ LinuxBIOS should restart HERE ] > HyperT reset not needed > PCI: pci_scan_bus for bus 1 > PCI: 01:01.0 [1022/7454] ops [..] Stefan -- Architecture Team SuSE Linux AG _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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flash_and_burn patch
by Niki Waibel 11 Sep '03

11 Sep '03

hello, i cleaned up the util/flash_and_burn dir of linuxbios cvs 20030910. everyting compiles without warnings now. i am about to add support for the msystems doc device chips. who actually maintains the util/flash_and_burn tree? i could not find any email address in the files. i am going to post a patch === $ ls -la flash_and_burn_20030910.patch.bz2 -rw-r----- 1 nwaibel staff 5539 2003-09-11 12:13 flash_and_burn_20030910.patch.bz2 === to this list if noone complains within the next 20 minutes. niki

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