Thanks to ron I made an romimage that is the right size, without um commenting out code here and there ;). LinuxBIOS was built fine, comes up sort of. Here's the logfile. I used FILO as my payload and well it can't find the device hda1... I've tried it with FILO 0.3 and 0.2, and get the same results... Here is the output... its long but well sorry ;)
On a side note, I'm unusually happy at the fact that V2 can reboot the system without my intervention... small things seem great sometimes.
Anyway, any ideas what the problem is or where to look?
***** V2 With FILO-0.3 ***** 0
LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing dimms_write: a55a5aa5 dimms_write: b55a5aa5 dimms_write: c55a5aa5 dimms_write: d55a5aa5 dimms_write: e55a5aa5 dimms_write: f55a5aa5 NOP dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 PRECHARGE DUMMY READS dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 CBR dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 MRS dimms_read: 000001d0 dimms_read: 100001d0 dimms_read: 200001d0 dimms_read: 300001d0 dimms_read: 400001d0 dimms_read: 500001d0 NORMAL dimms_write: 55aa55aa dimms_write: 65aa55aa dimms_write: 75aa55aa dimms_write: 85aa55aa dimms_write: 95aa55aa dimms_write: a5aa55aa dimms_read: 00000000 dimms_read: 10000000 dimms_read: 20000000 dimms_read: 30000000 dimms_read: 40000000 dimms_read: 50000000 set ref. rate enable multi-page open 00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00 10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50:ac 08 80 00 00 00 ff ff 40 00 ff ff ff ff ff ff 60:3f 00 00 30 e4 e4 e4 00 42 ac 65 0d 08 7f 00 00 70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00 80:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00 b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00 MA write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee write to 0 write to 8 done write to eax done read to eax eax and esi: 02000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 done write to eax done read to eax eax and esi: 04000000 00000000 enabled first bank of ram ... ma is ee vt8601 done 00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00 10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50:ac 08 80 00 00 00 28 28 ee 00 28 28 28 28 28 28 60:3f 00 00 30 e4 e4 e4 00 42 ac 65 0d 08 7f 00 00 70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00 80:00 c1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00 b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 starting... Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.4.0Fallback Wed Oct 8 11:47:14 MDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: VIA vt8601 Northbridge Enumerating: VIA vt8231 Enumerating buses...mainboard_scan_bus: root 0000c4a0 maxbus 0 PCI: pci_scan_bus for bus 0 Read config 32 bus 0,devfn 0x0,reg 0x0,val 0x6011106 malloc Enter, size 252, free_mem_ptr 00014308 malloc 0x00014308 Read config 8 bus 0,devfn 0x0,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x8,val 0x6000005 PCI: 00:00.0 [1106/0601] enabled Read config 32 bus 0,devfn 0x8,reg 0x0,val 0x86011106 malloc Enter, size 252, free_mem_ptr 00014404 malloc 0x00014404 Read config 8 bus 0,devfn 0x8,reg 0xe,val 0x1 Read config 32 bus 0,devfn 0x8,reg 0x8,val 0x6040000 PCI: 00:01.0 [1106/8601] enabled Read config 32 bus 0,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 0,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 0,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 0,devfn 0x28,reg 0x0,val 0xffffffff PCI: devfn 0x28, bad id 0xffffffff Read config 32 bus 0,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 0,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 0,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 0,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 0,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 0,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 0,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 0,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 0,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 0,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 0,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x0,val 0x82311106 malloc Enter, size 252, free_mem_ptr 00014500 malloc 0x00014500 Read config 8 bus 0,devfn 0x88,reg 0xe,val 0x80 Read config 32 bus 0,devfn 0x88,reg 0x8,val 0x6010010 PCI: 00:11.0 [1106/8231] enabled Read config 32 bus 0,devfn 0x89,reg 0x0,val 0x5711106 malloc Enter, size 252, free_mem_ptr 000145fc malloc 0x000145fc Read config 8 bus 0,devfn 0x89,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x8,val 0x1018f06 PCI: 00:11.1 [1106/0571] enabled Read config 32 bus 0,devfn 0x8a,reg 0x0,val 0x30381106 malloc Enter, size 252, free_mem_ptr 000146f8 malloc 0x000146f8 Read config 8 bus 0,devfn 0x8a,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x8,val 0xc03001e PCI: 00:11.2 [1106/3038] enabled Read config 32 bus 0,devfn 0x8b,reg 0x0,val 0x30381106 malloc Enter, size 252, free_mem_ptr 000147f4 malloc 0x000147f4 Read config 8 bus 0,devfn 0x8b,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x8,val 0xc03001e PCI: 00:11.3 [1106/3038] enabled Read config 32 bus 0,devfn 0x8c,reg 0x0,val 0x82351106 malloc Enter, size 252, free_mem_ptr 000148f0 malloc 0x000148f0 Read config 8 bus 0,devfn 0x8c,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x8,val 0x10 PCI: 00:11.4 [1106/8235] enabled Read config 32 bus 0,devfn 0x8d,reg 0x0,val 0x30581106 malloc Enter, size 252, free_mem_ptr 000149ec malloc 0x000149ec Read config 8 bus 0,devfn 0x8d,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x8,val 0x4010040 PCI: 00:11.5 [1106/3058] enabled Read config 32 bus 0,devfn 0x8e,reg 0x0,val 0x30681106 malloc Enter, size 252, free_mem_ptr 00014ae8 malloc 0x00014ae8 Read config 8 bus 0,devfn 0x8e,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x8,val 0x7800020 PCI: 00:11.6 [1106/3068] enabled Read config 32 bus 0,devfn 0x8f,reg 0x0,val 0xffffffff PCI: devfn 0x8f, bad id 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x0,val 0x30651106 malloc Enter, size 252, free_mem_ptr 00014be4 malloc 0x00014be4 Read config 8 bus 0,devfn 0x90,reg 0xe,val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x8,val 0x2000051 PCI: 00:12.0 [1106/3065] enabled Read config 32 bus 0,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 0,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 0,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 0,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 0,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 0,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 0,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 0,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 0,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 0,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 0,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 0,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 0,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff pci_scan_bridge: dev 00014404, max 0 Read config 16 bus 0,devfn 0x8,reg 0x4,val 0x7 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x0 Write config 16 bus 0, devfn 0x8, reg 0x6, val 0xffff Read config 32 bus 0,devfn 0x8,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x18, val 0xff0100 PCI: pci_scan_bus for bus 1 Read config 32 bus 1,devfn 0x0,reg 0x0,val 0xffffffff PCI: devfn 0x0, bad id 0xffffffff Read config 32 bus 1,devfn 0x8,reg 0x0,val 0xffffffff PCI: devfn 0x8, bad id 0xffffffff Read config 32 bus 1,devfn 0x10,reg 0x0,val 0xffffffff PCI: devfn 0x10, bad id 0xffffffff Read config 32 bus 1,devfn 0x18,reg 0x0,val 0xffffffff PCI: devfn 0x18, bad id 0xffffffff Read config 32 bus 1,devfn 0x20,reg 0x0,val 0xffffffff PCI: devfn 0x20, bad id 0xffffffff Read config 32 bus 1,devfn 0x28,reg 0x0,val 0xffffffff PCI: devfn 0x28, bad id 0xffffffff Read config 32 bus 1,devfn 0x30,reg 0x0,val 0xffffffff PCI: devfn 0x30, bad id 0xffffffff Read config 32 bus 1,devfn 0x38,reg 0x0,val 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Read config 32 bus 1,devfn 0x40,reg 0x0,val 0xffffffff PCI: devfn 0x40, bad id 0xffffffff Read config 32 bus 1,devfn 0x48,reg 0x0,val 0xffffffff PCI: devfn 0x48, bad id 0xffffffff Read config 32 bus 1,devfn 0x50,reg 0x0,val 0xffffffff PCI: devfn 0x50, bad id 0xffffffff Read config 32 bus 1,devfn 0x58,reg 0x0,val 0xffffffff PCI: devfn 0x58, bad id 0xffffffff Read config 32 bus 1,devfn 0x60,reg 0x0,val 0xffffffff PCI: devfn 0x60, bad id 0xffffffff Read config 32 bus 1,devfn 0x68,reg 0x0,val 0xffffffff PCI: devfn 0x68, bad id 0xffffffff Read config 32 bus 1,devfn 0x70,reg 0x0,val 0xffffffff PCI: devfn 0x70, bad id 0xffffffff Read config 32 bus 1,devfn 0x78,reg 0x0,val 0xffffffff PCI: devfn 0x78, bad id 0xffffffff Read config 32 bus 1,devfn 0x80,reg 0x0,val 0xffffffff PCI: devfn 0x80, bad id 0xffffffff Read config 32 bus 1,devfn 0x88,reg 0x0,val 0xffffffff PCI: devfn 0x88, bad id 0xffffffff Read config 32 bus 1,devfn 0x90,reg 0x0,val 0xffffffff PCI: devfn 0x90, bad id 0xffffffff Read config 32 bus 1,devfn 0x98,reg 0x0,val 0xffffffff PCI: devfn 0x98, bad id 0xffffffff Read config 32 bus 1,devfn 0xa0,reg 0x0,val 0xffffffff PCI: devfn 0xa0, bad id 0xffffffff Read config 32 bus 1,devfn 0xa8,reg 0x0,val 0xffffffff PCI: devfn 0xa8, bad id 0xffffffff Read config 32 bus 1,devfn 0xb0,reg 0x0,val 0xffffffff PCI: devfn 0xb0, bad id 0xffffffff Read config 32 bus 1,devfn 0xb8,reg 0x0,val 0xffffffff PCI: devfn 0xb8, bad id 0xffffffff Read config 32 bus 1,devfn 0xc0,reg 0x0,val 0xffffffff PCI: devfn 0xc0, bad id 0xffffffff Read config 32 bus 1,devfn 0xc8,reg 0x0,val 0xffffffff PCI: devfn 0xc8, bad id 0xffffffff Read config 32 bus 1,devfn 0xd0,reg 0x0,val 0xffffffff PCI: devfn 0xd0, bad id 0xffffffff Read config 32 bus 1,devfn 0xd8,reg 0x0,val 0xffffffff PCI: devfn 0xd8, bad id 0xffffffff Read config 32 bus 1,devfn 0xe0,reg 0x0,val 0xffffffff PCI: devfn 0xe0, bad id 0xffffffff Read config 32 bus 1,devfn 0xe8,reg 0x0,val 0xffffffff PCI: devfn 0xe8, bad id 0xffffffff Read config 32 bus 1,devfn 0xf0,reg 0x0,val 0xffffffff PCI: devfn 0xf0, bad id 0xffffffff Read config 32 bus 1,devfn 0xf8,reg 0x0,val 0xffffffff PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus returning with max=01 Write config 32 bus 0, devfn 0x8, reg 0x18, val 0x10100 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x7 pci_scan_bridge returns max 1 PCI: pci_scan_bus returning with max=01 DONE mainboard_scan_bus: return 0 done dev_configure: Allocating resources... root_dev_read_resources . Root is 0000c4a0 root_dev_read_resources . link 0000c560, resource 0000c4cc compute_allocate_resource: bus 0000c560, bridge 0000c4cc, type_mask 0x100, type 0x100 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_io: base: 00000400 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 pci_bridge_read_bases: path PCI: 00:01.0 compute_allocate_resource: bus 000144c4, bridge 00014430, type_mask 0x100, type 0x100 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 <null> compute_allocate_io: base: 00000000 size: 00000000 align: 12 gran: 12 done compute_allocate_resource: bus 000144c4, bridge 00014448, type_mask 0x1200, type 0x1200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done compute_allocate_resource: bus 000144c4, bridge 00014460, type_mask 0x1200, type 0x200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_mem: base: 00000000 size: 00000000 align: 20 gran: 20 done DONE pci_bridge_read_bases: path PCI: 00:01.0 Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8,reg 0x38,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x10,val 0x1f1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x10,val 0xfffffff9 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1f1 Read config 32 bus 0,devfn 0x89,reg 0x14,val 0x3f5 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x14,val 0xfffffffd Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x3f5 Read config 32 bus 0,devfn 0x89,reg 0x18,val 0x171 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x18,val 0xfffffff9 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x171 Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0x375 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0xfffffffd Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x1c,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x375 Read config 32 bus 0,devfn 0x89,reg 0x20,val 0xcc01 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x20,val 0xfffffff1 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xcc01 Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x89,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0xfce1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0xffffffe1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0xfce1 Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8a, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8a,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0xfce1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0xffffffe1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x20,val 0x1 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0xfce1 Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8b, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8b,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0xfffffffd Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x14,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0xfffffffd Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x18,val 0x1 Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x1 Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8d, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8d,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8e, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8e,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x10,val 0xffffff01 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x10,val 0x1 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x1 Read config 32 bus 0,devfn 0x90,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x14,val 0xffffff00 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x90, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x90,reg 0x30,val 0x0 PCI: 00:01.0 1c * [0x00001000 - 0x00000fff] io PCI: 00:11.5 10 * [0x00001000 - 0x000010ff] io PCI: 00:11.6 10 * [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 * [0x00001800 - 0x000018ff] io PCI: 00:11.2 20 * [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 * [0x00001c20 - 0x00001c3f] io PCI: 00:11.1 20 * [0x00001c40 - 0x00001c4f] io PCI: 00:11.1 10 * [0x00001c50 - 0x00001c57] io PCI: 00:11.1 18 * [0x00001c60 - 0x00001c67] io PCI: 00:11.1 14 * [0x00001c70 - 0x00001c73] io PCI: 00:11.1 1c * [0x00001c80 - 0x00001c83] io PCI: 00:11.5 14 * [0x00001c90 - 0x00001c93] io PCI: 00:11.5 18 * [0x00001ca0 - 0x00001ca3] io <null> compute_allocate_io: base: 00001ca4 size: 000018a4 align: 12 gran: 0 done root_dev_read_resources . link 0000c560, resource 0000c4e4 compute_allocate_resource: bus 0000c560, bridge 0000c4e4, type_mask 0x200, type 0x200 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_mem: base: 00000000 size: 00000000 align: 0 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 24 * [0x00000000 - 0xffffffff] prefmem PCI: 00:01.0 20 * [0x00000000 - 0xffffffff] mem PCI: 00:12.0 14 * [0x00000000 - 0x000000ff] mem <null> compute_allocate_mem: base: 00000100 size: 00000100 align: 20 gran: 0 done root_dev_read_resources DONE dev_configure: done reading resources... compute_allocate_resource: bus 0000c560, bridge 0000c4cc, type_mask 0x100, type 0x100 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_io: base: 00001000 size: 000018a4 align: 12 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 1c * [0x00001000 - 0x00000fff] io PCI: 00:11.5 10 * [0x00001000 - 0x000010ff] io PCI: 00:11.6 10 * [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 * [0x00001800 - 0x000018ff] io PCI: 00:11.2 20 * [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 * [0x00001c20 - 0x00001c3f] io PCI: 00:11.1 20 * [0x00001c40 - 0x00001c4f] io PCI: 00:11.1 10 * [0x00001c50 - 0x00001c57] io PCI: 00:11.1 18 * [0x00001c60 - 0x00001c67] io PCI: 00:11.1 14 * [0x00001c70 - 0x00001c73] io PCI: 00:11.1 1c * [0x00001c80 - 0x00001c83] io PCI: 00:11.5 14 * [0x00001c90 - 0x00001c93] io PCI: 00:11.5 18 * [0x00001ca0 - 0x00001ca3] io <null> compute_allocate_io: base: 00001ca4 size: 00000ca4 align: 12 gran: 0 done compute_allocate_resource: bus 0000c560, bridge 0000c4e4, type_mask 0x200, type 0x200 vendor 0x0 device 0x0 class 0x0 Unknown device path type: 0 compute_allocate_mem: base: feb00000 size: 00000100 align: 20 gran: 0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x10,val 0x8 Write config 32 bus 0, devfn 0x0, reg 0x10, val 0x8 PCI: 00:00.0 register 10(00000008), read-only ignoring it Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x0, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x0,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x88, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x88,reg 0x30,val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x10,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x10, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x14,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x14, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x18,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x18, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x1c,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x1c, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x20,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x20, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0xffffffff Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x24,val 0x0 Write config 32 bus 0, devfn 0x8c, reg 0x24, val 0x0 Read config 32 bus 0,devfn 0x8c,reg 0x30,val 0x0 PCI: 00:01.0 24 * [0xfeb00000 - 0xfeafffff] prefmem PCI: 00:01.0 20 * [0xfeb00000 - 0xfeafffff] mem PCI: 00:12.0 14 * [0xfeb00000 - 0xfeb000ff] mem <null> compute_allocate_mem: base: feb00100 size: 00000100 align: 20 gran: 0 done ASSIGN RESOURCES, bus 0 Write config 8 bus 0, devfn 0x0, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x0,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x0, reg 0xc, val 0x10 compute_allocate_resource: bus 000144c4, bridge 00014430, type_mask 0x100, type 0x100 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_io: base: 00001000 size: 00000000 align: 12 gran: 12 <null> compute_allocate_io: base: 00001000 size: 00000000 align: 12 gran: 12 done Write config 8 bus 0, devfn 0x8, reg 0x1c, val 0x10 Write config 8 bus 0, devfn 0x8, reg 0x1d, val 0xf Write config 16 bus 0, devfn 0x8, reg 0x30, val 0x0 Write config 16 bus 0, devfn 0x8, reg 0x32, val 0x0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io compute_allocate_resource: bus 000144c4, bridge 00014448, type_mask 0x1200, type 0x1200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_prefmem: base: feb00000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_prefmem: base: feb00000 size: 00000000 align: 20 gran: 20 done Write config 16 bus 0, devfn 0x8, reg 0x24, val 0xfeb0 Write config 16 bus 0, devfn 0x8, reg 0x26, val 0xfeaf Write config 32 bus 0, devfn 0x8, reg 0x28, val 0x0 Write config 32 bus 0, devfn 0x8, reg 0x2c, val 0x0 PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem compute_allocate_resource: bus 000144c4, bridge 00014460, type_mask 0x1200, type 0x200 vendor 0x1106 device 0x8601 class 0x60400 PCI: 00:01.0 compute_allocate_mem: base: feb00000 size: 00000000 align: 20 gran: 20 <null> compute_allocate_mem: base: feb00000 size: 00000000 align: 20 gran: 20 done Write config 16 bus 0, devfn 0x8, reg 0x20, val 0xfeb0 Write config 16 bus 0, devfn 0x8, reg 0x22, val 0xfeaf PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem Write config 8 bus 0, devfn 0x8, reg 0xd, val 0x40 Write config 8 bus 0, devfn 0x8, reg 0x1b, val 0x40 Read config 8 bus 0,devfn 0x8,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x8, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0x88, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1c51 PCI: 00:11.1 10 <- [0x00001c50 - 0x00001c57] io Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x1c71 PCI: 00:11.1 14 <- [0x00001c70 - 0x00001c73] io Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x1c61 PCI: 00:11.1 18 <- [0x00001c60 - 0x00001c67] io Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x1c81 PCI: 00:11.1 1c <- [0x00001c80 - 0x00001c83] io Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x1c41 PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io Write config 8 bus 0, devfn 0x89, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x89, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8a, reg 0x20, val 0x1c01 PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io Write config 8 bus 0, devfn 0x8a, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8a, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8b, reg 0x20, val 0x1c21 PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io Write config 8 bus 0, devfn 0x8b, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8b, reg 0xc, val 0x10 Write config 8 bus 0, devfn 0x8c, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Write config 8 bus 0, devfn 0x8c, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8d, reg 0x10, val 0x1001 PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io Write config 32 bus 0, devfn 0x8d, reg 0x14, val 0x1c91 PCI: 00:11.5 14 <- [0x00001c90 - 0x00001c93] io Write config 32 bus 0, devfn 0x8d, reg 0x18, val 0x1ca1 PCI: 00:11.5 18 <- [0x00001ca0 - 0x00001ca3] io Write config 8 bus 0, devfn 0x8d, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8d, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x8e, reg 0x10, val 0x1401 PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io Write config 8 bus 0, devfn 0x8e, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x8e, reg 0xc, val 0x10 Write config 32 bus 0, devfn 0x90, reg 0x10, val 0x1801 PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io Write config 32 bus 0, devfn 0x90, reg 0x14, val 0xfeb00000 PCI: 00:12.0 14 <- [0xfeb00000 - 0xfeb000ff] mem Write config 8 bus 0, devfn 0x90, reg 0xd, val 0x40 Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0x0 Write config 8 bus 0, devfn 0x90, reg 0xc, val 0x10 ASSIGNED RESOURCES, bus 0 dev_configure: done setting resources... dev_configure: done vga resources... done. Enabling resourcess... Read config 16 bus 0,devfn 0x0,reg 0x4,val 0x6 PCI: 00:00.0 cmd <- 06 Write config 16 bus 0, devfn 0x0, reg 0x4, val 0x6 Read config 16 bus 0,devfn 0x8,reg 0x3e,val 0x0 PCI: 00:01.0 bridge ctrl <- 0000 Write config 16 bus 0, devfn 0x8, reg 0x3e, val 0x0 Read config 16 bus 0,devfn 0x8,reg 0x4,val 0x7 PCI: 00:01.0 cmd <- 07 Write config 16 bus 0, devfn 0x8, reg 0x4, val 0x7 Read config 16 bus 0,devfn 0x88,reg 0x4,val 0x87 PCI: 00:11.0 cmd <- 87 Write config 16 bus 0, devfn 0x88, reg 0x4, val 0x87 Read config 16 bus 0,devfn 0x89,reg 0x4,val 0x80 PCI: 00:11.1 cmd <- 81 Write config 16 bus 0, devfn 0x89, reg 0x4, val 0x81 Read config 16 bus 0,devfn 0x8a,reg 0x4,val 0x0 PCI: 00:11.2 cmd <- 01 Write config 16 bus 0, devfn 0x8a, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8b,reg 0x4,val 0x0 PCI: 00:11.3 cmd <- 01 Write config 16 bus 0, devfn 0x8b, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8c,reg 0x4,val 0x0 PCI: 00:11.4 cmd <- 00 Write config 16 bus 0, devfn 0x8c, reg 0x4, val 0x0 Read config 16 bus 0,devfn 0x8d,reg 0x4,val 0x0 PCI: 00:11.5 cmd <- 01 Write config 16 bus 0, devfn 0x8d, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x8e,reg 0x4,val 0x0 PCI: 00:11.6 cmd <- 01 Write config 16 bus 0, devfn 0x8e, reg 0x4, val 0x1 Read config 16 bus 0,devfn 0x90,reg 0x4,val 0x80 PCI: 00:12.0 cmd <- 83 Write config 16 bus 0, devfn 0x90, reg 0x4, val 0x83 done. Initializing devices... Devices initialized vt8231 init Read config 8 bus 0,devfn 0x88,reg 0x6c,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x6c, val 0x80 Write config 8 bus 0, devfn 0x88, reg 0x41, val 0x7f Read config 8 bus 0,devfn 0x88,reg 0x40,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x40, val 0x0 Read config 8 bus 0,devfn 0x88,reg 0x42,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x42, val 0xf0 Read config 8 bus 0,devfn 0x88,reg 0x4a,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x4a, val 0x8 Read config 8 bus 0,devfn 0x88,reg 0x4f,val 0x0 Write config 8 bus 0, devfn 0x88, reg 0x4f, val 0x8 Write config 8 bus 0, devfn 0x88, reg 0x58, val 0x3 Read config 8 bus 0,devfn 0x88,reg 0x51,val 0xff Write config 8 bus 0, devfn 0x88, reg 0x51, val 0xff Read config 8 bus 0,devfn 0x88,reg 0x6e,val 0x0 Read config 8 bus 0,devfn 0x88,reg 0x50,val 0x7 IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 Write config 8 bus 0, devfn 0x88, reg 0x50, val 0x7 Read config 8 bus 0,devfn 0x88,reg 0x4c,val 0x4 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 Write config 8 bus 0, devfn 0x88, reg 0x4c, val 0x4 Write config 8 bus 0, devfn 0x88, reg 0x46, val 0x4 Write config 8 bus 0, devfn 0x88, reg 0x47, val 0x3 Write config 8 bus 0, devfn 0x88, reg 0x6e, val 0x98 Write config 32 bus 0, devfn 0x8c, reg 0x48, val 0x4001 Write config 8 bus 0, devfn 0x8c, reg 0x41, val 0x84 Write config 32 bus 0, devfn 0x8c, reg 0x70, val 0x6001 Write config 8 bus 0, devfn 0x8c, reg 0x74, val 0x1 Write config 32 bus 0, devfn 0x8c, reg 0x90, val 0x5001 Write config 8 bus 0, devfn 0x8c, reg 0xd2, val 0x1 vt8231_init: enabling native IDE addresses Read config 8 bus 0,devfn 0x89,reg 0x42,val 0xc9 enables in reg 0x42 0xc9 Write config 8 bus 0, devfn 0x89, reg 0x42, val 0x9 Read config 8 bus 0,devfn 0x89,reg 0x42,val 0x9 enables in reg 0x42 read back as 0x9 Read config 8 bus 0,devfn 0x89,reg 0x40,val 0x8 enables in reg 0x40 0x8 Write config 8 bus 0, devfn 0x89, reg 0x40, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x40,val 0xb enables in reg 0x40 read back as 0xb Read config 8 bus 0,devfn 0x89,reg 0x41,val 0x2 Write config 8 bus 0, devfn 0x89, reg 0x41, val 0xf2 Read config 8 bus 0,devfn 0x89,reg 0x43,val 0x3a Write config 8 bus 0, devfn 0x89, reg 0x43, val 0x35 Write config 8 bus 0, devfn 0x89, reg 0x44, val 0x18 Write config 8 bus 0, devfn 0x89, reg 0x45, val 0x1c Read config 8 bus 0,devfn 0x89,reg 0x9,val 0x8f enables in reg 0x9 0x8f Write config 8 bus 0, devfn 0x89, reg 0x9, val 0x8f Read config 8 bus 0,devfn 0x89,reg 0x9,val 0x8f enables in reg 0x9 read back as 0x8f Read config 8 bus 0,devfn 0x89,reg 0x4,val 0x81 command in reg 0x4 0x81 Write config 8 bus 0, devfn 0x89, reg 0x4, val 0x7 Read config 8 bus 0,devfn 0x89,reg 0x4,val 0x7 command in reg 0x4 reads back as 0x7 Write config 8 bus 0, devfn 0x88, reg 0x40, val 0x54 Ethernet fixup Configuring VIA LAN Read config 8 bus 0,devfn 0x90,reg 0x4,val 0x83 Write config 8 bus 0, devfn 0x90, reg 0x4, val 0x3 RTC Init Invalid CMOS LB checksum FUCK! ROUTING FIXUP! pci_routing_fixup: dev is 00014500 Write config 8 bus 0, devfn 0x88, reg 0x55, val 0xb0 Write config 8 bus 0, devfn 0x88, reg 0x56, val 0xa5 Write config 8 bus 0, devfn 0x88, reg 0x57, val 0xc0 setting southbridge Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:11.1 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x3c,val 0xe Readback = 14 pci_level_irq: current ints are 0x0 pci_level_irq: try to set ints 0x800 Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.2 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8a,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x800 pci_level_irq: try to set ints 0x1800 pci_level_irq: lower order bits are wrong: want 0x8, got 0x18 Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.3 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8b,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1800 pci_level_irq: try to set ints 0x1800 pci_level_irq: lower order bits are wrong: want 0x8, got 0x18 Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.5 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8d,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1800 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.6 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8e,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting ethernet Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:12.0 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x90,reg 0x3c,val 0xb Readback = 11 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot pci_routing_fixup: DONE Read config 8 bus 0,devfn 0x0,reg 0x5a,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5b,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5c,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5d,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5e,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x5f,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x56,val 0x28 Read config 8 bus 0,devfn 0x0,reg 0x57,val 0x28 I would set ram size to 0x50000 Kbytes mem[0].basek = 00000000 mem[0].sizek = 00050000 mem[1].basek = 00000000 mem[1].sizek = 00000000 mem[2].basek = 00000000 mem[2].sizek = 00000000 mem[3].basek = 00000000 mem[3].sizek = 00000000 mem[4].basek = 00000000 mem[4].sizek = 00000000 mem[5].basek = 00000000 mem[5].sizek = 00000000 mem[6].basek = 00000000 mem[6].sizek = 00000000 mem[7].basek = 00000000 mem[7].sizek = 00000000 mem[8].basek = 00000000 mem[8].sizek = 00000000 mem[9].basek = 00000000 mem[9].sizek = 00000000 totalram: 320M Initializing CPU #0 Updating microcode microcode_info: sig = 0x00000673 pf=0x00000001 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB Setting variable MTRR 1, base: 256MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done.
Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized BOOT CPU is 0 Checking IRQ routing tables... /usr/src/freebios2/src/arch/i386/boot/pirq_routing.c: 29:check_pirq_routing_table() - irq_routing_table located at: 0x0000a020 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed Wrote linuxbios table at: 00000500 - 00000ae0 checksum e367 VT8601 random fixup ... Write config 8 bus 0, devfn 0x0, reg 0x70, val 0xc0 Write config 8 bus 0, devfn 0x0, reg 0x71, val 0x88 Write config 8 bus 0, devfn 0x0, reg 0x72, val 0xec Write config 8 bus 0, devfn 0x0, reg 0x73, val 0xc Write config 8 bus 0, devfn 0x0, reg 0x74, val 0xe Write config 8 bus 0, devfn 0x0, reg 0x75, val 0x81 Write config 8 bus 0, devfn 0x0, reg 0x76, val 0x52 pci_routing_fixup: dev is 00014500 Write config 8 bus 0, devfn 0x88, reg 0x55, val 0xb0 Write config 8 bus 0, devfn 0x88, reg 0x56, val 0xa5 Write config 8 bus 0, devfn 0x88, reg 0x57, val 0xc0 setting southbridge Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x89,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:11.1 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x89,reg 0x3c,val 0xe Readback = 14 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8a,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.2 Write config 8 bus 0, devfn 0x8a, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8a,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8b,reg 0x3d,val 0x4 Assigning IRQ 12 to 0:11.3 Write config 8 bus 0, devfn 0x8b, reg 0x3c, val 0xc Read config 8 bus 0,devfn 0x8b,reg 0x3c,val 0xc Readback = 12 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8c,reg 0x3d,val 0x0 Read config 8 bus 0,devfn 0x8d,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.5 Write config 8 bus 0, devfn 0x8d, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8d,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c Read config 8 bus 0,devfn 0x8e,reg 0x3d,val 0x3 Assigning IRQ 10 to 0:11.6 Write config 8 bus 0, devfn 0x8e, reg 0x3c, val 0xa Read config 8 bus 0,devfn 0x8e,reg 0x3c,val 0xa Readback = 10 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting ethernet Read config 8 bus 0,devfn 0x90,reg 0x3d,val 0x1 Assigning IRQ 11 to 0:12.0 Write config 8 bus 0, devfn 0x90, reg 0x3c, val 0xb Read config 8 bus 0,devfn 0x90,reg 0x3c,val 0xb Readback = 11 pci_level_irq: current ints are 0x1c00 pci_level_irq: try to set ints 0x1c00 pci_level_irq: lower order bits are wrong: want 0xc, got 0x1c setting pci slot pci_routing_fixup: DONE 0x0: Read config 8 bus 0,devfn 0x88,reg 0x0,val 0x6 06 Read config 8 bus 0,devfn 0x88,reg 0x1,val 0x11 11 Read config 8 bus 0,devfn 0x88,reg 0x2,val 0x31 31 Read config 8 bus 0,devfn 0x88,reg 0x3,val 0x82 82 Read config 8 bus 0,devfn 0x88,reg 0x4,val 0x87 87 Read config 8 bus 0,devfn 0x88,reg 0x5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6,val 0x10 10 Read config 8 bus 0,devfn 0x88,reg 0x7,val 0x2 02 Read config 8 bus 0,devfn 0x88,reg 0x8,val 0x10 10 Read config 8 bus 0,devfn 0x88,reg 0x9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0xb,val 0x6 06 Read config 8 bus 0,devfn 0x88,reg 0xc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe,val 0x80 80 Read config 8 bus 0,devfn 0x88,reg 0xf,val 0x0 00 0x10: Read config 8 bus 0,devfn 0x88,reg 0x10,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x11,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x12,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x13,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x14,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x15,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x16,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x17,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x18,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x19,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x1f,val 0x0 00 0x20: Read config 8 bus 0,devfn 0x88,reg 0x20,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x21,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x22,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x23,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x24,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x25,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x26,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x27,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x28,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x29,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x2f,val 0x0 00 0x30: Read config 8 bus 0,devfn 0x88,reg 0x30,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x31,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x32,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x33,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x34,val 0xc0 c0 Read config 8 bus 0,devfn 0x88,reg 0x35,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x36,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x37,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x38,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x39,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x3f,val 0x0 00 0x40: Read config 8 bus 0,devfn 0x88,reg 0x40,val 0x54 54 Read config 8 bus 0,devfn 0x88,reg 0x41,val 0x7f 7f Read config 8 bus 0,devfn 0x88,reg 0x42,val 0xf0 f0 Read config 8 bus 0,devfn 0x88,reg 0x43,val 0x20 20 Read config 8 bus 0,devfn 0x88,reg 0x44,val 0x4e 4e Read config 8 bus 0,devfn 0x88,reg 0x45,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x46,val 0x4 04 Read config 8 bus 0,devfn 0x88,reg 0x47,val 0x3 03 Read config 8 bus 0,devfn 0x88,reg 0x48,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x49,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4a,val 0x8 08 Read config 8 bus 0,devfn 0x88,reg 0x4b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4c,val 0x4 04 Read config 8 bus 0,devfn 0x88,reg 0x4d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x4f,val 0x8 08 0x50: Read config 8 bus 0,devfn 0x88,reg 0x50,val 0x7 07 Read config 8 bus 0,devfn 0x88,reg 0x51,val 0xff ff Read config 8 bus 0,devfn 0x88,reg 0x52,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x53,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x54,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x55,val 0xb0 b0 Read config 8 bus 0,devfn 0x88,reg 0x56,val 0xa5 a5 Read config 8 bus 0,devfn 0x88,reg 0x57,val 0xc0 c0 Read config 8 bus 0,devfn 0x88,reg 0x58,val 0x3 03 Read config 8 bus 0,devfn 0x88,reg 0x59,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x5f,val 0x0 00 0x60: Read config 8 bus 0,devfn 0x88,reg 0x60,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x61,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x62,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x63,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x64,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x65,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x66,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x67,val 0x8 08 Read config 8 bus 0,devfn 0x88,reg 0x68,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0x69,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6c,val 0x80 80 Read config 8 bus 0,devfn 0x88,reg 0x6d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x6e,val 0x98 98 Read config 8 bus 0,devfn 0x88,reg 0x6f,val 0x0 00 0x70: Read config 8 bus 0,devfn 0x88,reg 0x70,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x71,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x72,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x73,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x74,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x75,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x76,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x77,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x78,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x79,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7c,val 0x20 20 Read config 8 bus 0,devfn 0x88,reg 0x7d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x7f,val 0x0 00 0x80: Read config 8 bus 0,devfn 0x88,reg 0x80,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x81,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x82,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x83,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x84,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x85,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x86,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x87,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x88,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x89,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x8f,val 0x0 00 0x90: Read config 8 bus 0,devfn 0x88,reg 0x90,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x91,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x92,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x93,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x94,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x95,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x96,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x97,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x98,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x99,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9a,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9b,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9c,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9d,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9e,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0x9f,val 0x0 00 0xa0: Read config 8 bus 0,devfn 0x88,reg 0xa0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xa9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xaa,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xab,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xac,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xad,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xae,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xaf,val 0x0 00 0xb0: Read config 8 bus 0,devfn 0x88,reg 0xb0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xb9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xba,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbe,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xbf,val 0x0 00 0xc0: Read config 8 bus 0,devfn 0x88,reg 0xc0,val 0x1 01 Read config 8 bus 0,devfn 0x88,reg 0xc1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc2,val 0x2 02 Read config 8 bus 0,devfn 0x88,reg 0xc3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xc9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xca,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xce,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xcf,val 0x0 00 0xd0: Read config 8 bus 0,devfn 0x88,reg 0xd0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xd9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xda,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xde,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xdf,val 0x0 00 0xe0: Read config 8 bus 0,devfn 0x88,reg 0xe0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe6,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xe9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xea,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xeb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xec,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xed,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xee,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xef,val 0x0 00 0xf0: Read config 8 bus 0,devfn 0x88,reg 0xf0,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf1,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf2,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf3,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf4,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf5,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf6,val 0x15 15 Read config 8 bus 0,devfn 0x88,reg 0xf7,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf8,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xf9,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfa,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfb,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfc,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfd,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xfe,val 0x0 00 Read config 8 bus 0,devfn 0x88,reg 0xff,val 0x0 00
Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3
23:stream_init() - rom_stream: 0xfffc0000 - 0xfffeffff Found ELF candiate at offset 0 header_offset is 0 Try to load at offset 0x0 malloc Enter, size 32, free_mem_ptr 00014ce0 malloc 0x00014ce0 New segment addr 0x100000 size 0x1fd70 offset 0xa0 filesize 0x66e8 (cleaned up) New segment addr 0x100000 size 0x1fd70 offset 0xa0 filesize 0x66e8 lb: [0x0000000000004000, 0x0000000000018308) malloc Enter, size 32, free_mem_ptr 00014d00 malloc 0x00014d00 New segment addr 0x11fd80 size 0x48 offset 0x67a0 filesize 0x48 (cleaned up) New segment addr 0x11fd80 size 0x48 offset 0x67a0 filesize 0x48 lb: [0x0000000000004000, 0x0000000000018308) Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000001fd70 filesz: 0x00000000000066e8 [ 0x0000000000100000, 00000000001066e8, 0x000000000011fd70) <- 00000000000000a0 Clearing Segment: addr: 0x00000000001066e8 memsz: 0x0000000000019688 Loading Segment: addr: 0x000000000011fd80 memsz: 0x0000000000000048 filesz: 0x0000000000000048 [ 0x000000000011fd80, 000000000011fdc8, 0x000000000011fdc8) <- 00000000000067a0 Loaded segments verified segments closed down stream Jumping to boot code at 0x104718 entry = 0x00104718 lb_start = 0x00004000 lb_size = 0x00014308 adjust = 0x13fe7cf8 buffer = 0x13fd79f0 elf_boot_notes = 0x0000dd60 adjusted_boot_notes = 0x13ff5a58 FILO version 0.3 (root@kioskdev) Tue Oct 7 18:37:11 MDT 2003 Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 Detected floating bus No such device boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 No such device
On 8 Oct 2003, Nathanael D. Noblet wrote:
Thanks to ron I made an romimage that is the right size, without um commenting out code here and there ;). LinuxBIOS was built fine, comes up sort of. Here's the logfile. I used FILO as my payload and well it can't find the device hda1... I've tried it with FILO 0.3 and 0.2, and get the same results... Here is the output... its long but well sorry ;)
thanks for the output!
Guess what? This is all my fault!
Well, actually, it is that although I am certain I am programming the IDE control registers correctly, FILO doesn't like what I have done:
Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 Detected floating bus
^^^^^^^^^^^^^^^^^^^^^
bad! bad! bad!
No such device boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 No such device
So, I will try to fix this, as I really want FILO working. I will try to figure this out tomorrow.
ron p.s. did you know that if you rearrange the letters of IDE, it spells DIE?
ron minnich rminnich@lanl.gov writes:
On 8 Oct 2003, Nathanael D. Noblet wrote:
Thanks to ron I made an romimage that is the right size, without um commenting out code here and there ;). LinuxBIOS was built fine, comes up sort of. Here's the logfile. I used FILO as my payload and well it can't find the device hda1... I've tried it with FILO 0.3 and 0.2, and get the same results... Here is the output... its long but well sorry ;)
thanks for the output!
Guess what? This is all my fault!
Well, actually, it is that although I am certain I am programming the IDE control registers correctly, FILO doesn't like what I have done:
The current device resource assignment code should cope with static resource assignments, so hopefully it should be a matter of plugging hard codes into the device tree.
If not please holler.
The hdama has exactly the same issue of using non legacy addresses, so this is a general freebios2 issue.
Although looking at that code there is another issue. You are using dev_find_device in vt8231.c inappropriately. dev_find_device should be virtually unnecessary in the freebios2 tree. Except when you are very carefully using dev_find_device will fail to handle multiple instances of a device. This is a very bad example to set when doing things properly causes everything to work transparently.
Press <Enter> for default boot, or <Esc> for boot prompt... 2 1 timed out boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 Detected floating bus
^^^^^^^^^^^^^^^^^^^^^
bad! bad! bad!
No such device boot: hda1:/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 No such device
So, I will try to fix this, as I really want FILO working. I will try to figure this out tomorrow.
This is also a limitation in FILO that it is scanning for devices only using the legacy port addresses. Using those addresses is great but this problem would have remained hidden if FILO did a scan through pci devices like etherboot does.
ron p.s. did you know that if you rearrange the letters of IDE, it spells DIE?
Well that would explain your initial disk on Pink.
Eric
On 8 Oct 2003, Eric W. Biederman wrote:
The current device resource assignment code should cope with static resource assignments, so hopefully it should be a matter of plugging hard codes into the device tree.
no, greg and I will be talking to you about this. There is a problem with that code, which I have alluded to, in that you can not (in the current system) do device assignments etc. before pci enumeration, and it is essential that you be able to do that.
Although looking at that code there is another issue. You are using dev_find_device in vt8231.c inappropriately. dev_find_device should be virtually unnecessary in the freebios2 tree. Except when you are very carefully using dev_find_device will fail to handle multiple instances of a device. This is a very bad example to set when doing things properly causes everything to work transparently.
legacy code. Has to get fixed.
Examples of proper usage welcomed. Although this actually points out a problem with the dynamic tree: it handles complex cases well, simple cases poorly. All I want to do is get into that device BEFORE pci enumeration and set some default values. You can't do that in the current scheme.
This is also a limitation in FILO that it is scanning for devices only using the legacy port addresses. Using those addresses is great but this problem would have remained hidden if FILO did a scan through pci devices like etherboot does.
yes.
ron
At 8:45 AM -0600 9/10/03, ron minnich wrote:
On 8 Oct 2003, Eric W. Biederman wrote:
The current device resource assignment code should cope with static resource assignments, so hopefully it should be a matter of plugging hard codes into the device tree.
no, greg and I will be talking to you about this. There is a problem with that code, which I have alluded to, in that you can not (in the current system) do device assignments etc. before pci enumeration, and it is essential that you be able to do that.
Although looking at that code there is another issue. You are using dev_find_device in vt8231.c inappropriately. dev_find_device should be virtually unnecessary in the freebios2 tree. Except when you are very carefully using dev_find_device will fail to handle multiple instances of a device. This is a very bad example to set when doing things properly causes everything to work transparently.
legacy code. Has to get fixed.
Examples of proper usage welcomed. Although this actually points out a problem with the dynamic tree: it handles complex cases well, simple cases poorly. All I want to do is get into that device BEFORE pci enumeration and set some default values. You can't do that in the current scheme.
Yes, I have a similar problem with the current setup. I need to be able to do static initialization on entry to hardwaremain, but before console_init(), and also prior to pci enumeration. Currently static device initialization can only be done during pci setup which is too late. I've started using chip_configure() again to get around this problem, but it means I have to skip the enumerate_static_devices() step or things go to hell.
Greg
Greg Watson gwatson@lanl.gov writes:
Yes, I have a similar problem with the current setup. I need to be able to do static initialization on entry to hardwaremain, but before console_init(), and also prior to pci enumeration.
The original conception was that such things would happen before hardwaremain was actually called. But regardless.
Currently static device initialization can only be done during pci setup which is too late.
Why???
I've started using chip_configure() again to get around this problem, but it means I have to skip the enumerate_static_devices() step or things go to hell.
Why???
I can feel that there is pain here. But I cannot see the source. There are two possible solutions. Either the current structure needs redesign or I need to more clearly document and explain the current structure so it can be fully taken advantage of.
So when you can please walk me through some specific problems so I can help resolve this issue.
Eric
On 9 Oct 2003, Eric W. Biederman wrote:
So when you can please walk me through some specific problems so I can help resolve this issue.
I'll try to get you something.
ron
At 12:11 PM -0600 9/10/03, Eric W. Biederman wrote:
Greg Watson gwatson@lanl.gov writes:
Yes, I have a similar problem with the current setup. I need to be able to do static initialization on entry to hardwaremain, but before console_init(), and also prior to pci enumeration.
The original conception was that such things would happen before hardwaremain was actually called. But regardless.
On the PPC, much of what must be done in assembly or romcc on Intel/AMD, can be done in C in hardwaremain. The architecture needs to be flexible enough to accommodate this.
Currently static device initialization can only be done during pci setup which is too late.
Why???
For example, I want to be able to configure the serial port on the superio chip so that console logging will work. This has to happen before console_init() is called. Other things that I want to be able to do that I don't want tied to PCI setup are:
- flash setup - NVRAM setup - on-board network interface setup - SDRAM setup
The order goes something like this:
hardwaremain() { pre_console: superio() console_init() pre_pci: nvram() sdram() flash() pci: pci() usb() ide() pre_boot: fenet() elfboot() }
In addition, I probably don't want to call cpu_initialize() after PCI setup. I would prefer if the cpu (or cpu's) was treated much the same as any other static device, then I could choose where cpu_init() gets called, which may be in multiple places.
I've started using chip_configure() again to get around this problem, but it means I have to skip the enumerate_static_devices() step or things go to hell.
Why???
Otherwise the chip initialization happens twice: once from the call to chip_configure() and once from dev_initialize(). And it happens at the wrong place.
I can feel that there is pain here. But I cannot see the source. There are two possible solutions. Either the current structure needs redesign or I need to more clearly document and explain the current structure so it can be fully taken advantage of.
The current design is too tied to PCI setup, doesn't provide any means of doing initialization other than when PCI devices are initialized and doesn't give any control over *when* devices are initialized. chip_configure() allows devices to choose when in the boot sequence they want to perform some action, and allows multiple actions to occur for a single device.
I'd be happy if the current scheme could provide this functionality, but I don't see any easy way to do it.
The fundamental problem I see is that Intel/AMD architectures do a lot more initialization prior to hardwaremain, so the functionality that I'm looking for is not really needed. Once you're in hardwaremain, basically all that's left to do is get PCI going. This is not the case for PPC (and maybe other architectures.) The question is really: should linuxbios be Intel/AMD specific and required other architecture support grafted on, or should it be made general enough to work with any architecture. I guess I'm suggesting the latter.
Greg
Greg Watson gwatson@lanl.gov writes:
At 12:11 PM -0600 9/10/03, Eric W. Biederman wrote:
Greg Watson gwatson@lanl.gov writes:
Yes, I have a similar problem with the current setup. I need to be able to do
static initialization on entry to hardwaremain, but before console_init(), and also prior to pci enumeration.
The original conception was that such things would happen before hardwaremain was actually called. But regardless.
On the PPC, much of what must be done in assembly or romcc on Intel/AMD, can be done in C in hardwaremain. The architecture needs to be flexible enough to accommodate this.
I concur. And the really weird stuff either needs to happen before we enter hardwaremain or as the first function we call. I have no problem with doing that. But it should be done that way because it is weird motherboard dependent code.
Currently static device initialization can only be done during pci setup which is too late.
Why???
For example, I want to be able to configure the serial port on the superio chip so that console logging will work. This has to happen before console_init() is called. Other things that I want to be able to do that I don't want tied to PCI setup are:
- flash setup
- NVRAM setup
- on-board network interface setup
- SDRAM setup
The order goes something like this:
hardwaremain() { pre_console: superio() console_init() pre_pci: nvram() sdram() flash() pci: pci() usb() ide() pre_boot: fenet() elfboot() }
Ok. If everything is working out of ram I can see modifying things so there is both a hook before console_init, and a hook after it so generic console code can be used. It is possible to define motherboard specific console drivers but proposing that as a solution to your problem is silly.
The ethernet case is not a case I currently understand. I would be highly surprised if something is needed there. My gut feel is a simple init method should be all that is needed. Unless you are doing an ethernet device driver and that is something else again.
In addition, I probably don't want to call cpu_initialize() after PCI setup. I would prefer if the cpu (or cpu's) was treated much the same as any other static device, then I could choose where cpu_init() gets called, which may be in multiple places.
I agree they way we are currently dealing with cpus is problematic, as it does not follow the same model as the rest of the code. There has not yet been much looking given to how to handle them correctly. Doing cpu initialization late has not mattered much because if you can run the code in C generally there are no show stopper cpu bugs or cpu setup that needs to be worried about.
I've started using chip_configure() again to get around this problem, but it means I have to skip the enumerate_static_devices() step or things go to hell.
Why???
Otherwise the chip initialization happens twice: once from the call to chip_configure() and once from dev_initialize(). And it happens at the wrong place.
There are two kinds of devices. Devices that are highly motherboard centric, and no matter what you do will have special rules and generic code cannot cope with them. And then there are devices that are well factored, and can be treated as independent pieces of hardware. The generic device tree is aimed at hardware that is well factored, for the rest we do need a different mechanism.
For a well factored device having it initialized at the wrong place is almost impossible. Except in the rare cases where the devices is needed to bootstrap another say the smbus controller for memory, and in those cases it is the memory or whatever else it is that is not a standalone device.
I can feel that there is pain here. But I cannot see the source. There are two possible solutions. Either the current structure needs redesign or I need to more clearly document and explain the current structure so it can be fully taken advantage of.
The current design is too tied to PCI setup.
I have to vent at this statement. Yes the code was derived from what is needed to setup PCI devices. But no it is not tied to PCI devices, and I believe this view is part of what is limiting this conversation. In particular I see no problem setting up superio I/O devices with this code.
I try and full fill a couple of requirements with the code. 1) Enable code reuse when the hardware is tied together on another board in a different way. 2) Enable flexible resource allocation. 3) If I have multiples of the device allow the code to just work.
For an individual device knowing specifically when it is initialized inspires brittle code.
If I have multiples of the same device the code needs to be able to hand out dynamic resource assignments.
And yes this results in a little bit of duplicate setup for hardware like a serial console that is both a generic piece of code and that must be bootstrapped early.
, doesn't provide any means of doing initialization other than when PCI devices are initialized and doesn't give any control over *when* devices are initialized.
It is assumed the dependencies can be represented in the device tree. If you are higher up in the tree you are initialized first. And of devices in the same level of the device tree the order in the static tree pretty much rules.
chip_configure() allows devices to choose when in the boot sequence they want to perform some action, and allows multiple actions to occur for a single device.
It also provides no structure and it solves none of the hard problems. As for being able to do things in the boot sequence I have 6 methods to your 8. Plenty of opportunity to do weird things if need be.
I guess what I would like to avoid is representing what is essentially a motherboard dependent function call graph in a static device tree instead of just doing it straight forwardly in C.
What I don't see with chip_configure is it promoting any level of code reuse because what the calls do is not well defined. They are called in relationship to other code instead of being called to do something.
I'd be happy if the current scheme could provide this functionality, but I don't see any easy way to do it.
Hmm.
The fundamental problem I see is that Intel/AMD architectures do a lot more initialization prior to hardwaremain, so the functionality that I'm looking for is not really needed.
I agree that the current x86 ports do a substantial amount prior to hardwaremain, and so we don't have a few of your issues. That can easily be rectified.
Once you're in hardwaremain, basically all that's left to do is get PCI going.
Not at all.
This is not the case for PPC (and maybe other architectures.) The question is really: should linuxbios be Intel/AMD specific and required other architecture support grafted on, or should it be made general enough to work with any architecture. I guess I'm suggesting the latter.
I totally agree with the sentiment. And if you don't have very many devices that need their addresses programmed dynamically.
Eric
In the interests of moving forward here, I will see if I can get this to work with dynamic device tree.
Greg
At 7:25 PM -0600 9/10/03, Eric W. Biederman wrote:
On the PPC, much of what must be done in assembly or romcc on
Intel/AMD, can be
done in C in hardwaremain. The architecture needs to be flexible enough to accommodate this.
I concur. And the really weird stuff either needs to happen before we enter hardwaremain or as the first function we call. I have no problem with doing that. But it should be done that way because it is weird motherboard dependent code.
For example, I want to be able to configure the serial port on
the superio chip
so that console logging will work. This has to happen before console_init() is called. Other things that I want to be able to do that I don't want tied to PCI setup are:
- flash setup
- NVRAM setup
- on-board network interface setup
- SDRAM setup
The order goes something like this:
hardwaremain() { pre_console: superio() console_init() pre_pci: nvram() sdram() flash() pci: pci() usb() ide() pre_boot: fenet() elfboot() }
Ok. If everything is working out of ram I can see modifying things so there is both a hook before console_init, and a hook after it so generic console code can be used. It is possible to define motherboard specific console drivers but proposing that as a solution to your problem is silly.
The ethernet case is not a case I currently understand. I would be highly surprised if something is needed there. My gut feel is a simple init method should be all that is needed. Unless you are doing an ethernet device driver and that is something else again.
In addition, I probably don't want to call cpu_initialize() after PCI setup. I would prefer if the cpu (or cpu's) was treated much the same as any other static device, then I could choose where cpu_init() gets called, which may be in multiple places.
I agree they way we are currently dealing with cpus is problematic, as it does not follow the same model as the rest of the code. There has not yet been much looking given to how to handle them correctly. Doing cpu initialization late has not mattered much because if you can run the code in C generally there are no show stopper cpu bugs or cpu setup that needs to be worried about.
Otherwise the chip initialization happens twice: once from the call to chip_configure() and once from dev_initialize(). And it happens at the wrong place.
There are two kinds of devices. Devices that are highly motherboard centric, and no matter what you do will have special rules and generic code cannot cope with them. And then there are devices that are well factored, and can be treated as independent pieces of hardware. The generic device tree is aimed at hardware that is well factored, for the rest we do need a different mechanism.
For a well factored device having it initialized at the wrong place is almost impossible. Except in the rare cases where the devices is needed to bootstrap another say the smbus controller for memory, and in those cases it is the memory or whatever else it is that is not a standalone device.
The current design is too tied to PCI setup.
I have to vent at this statement. Yes the code was derived from what is needed to setup PCI devices. But no it is not tied to PCI devices, and I believe this view is part of what is limiting this conversation. In particular I see no problem setting up superio I/O devices with this code.
I try and full fill a couple of requirements with the code.
- Enable code reuse when the hardware is tied together on another board in a different way.
- Enable flexible resource allocation.
- If I have multiples of the device allow the code to just work.
For an individual device knowing specifically when it is initialized inspires brittle code.
If I have multiples of the same device the code needs to be able to hand out dynamic resource assignments.
And yes this results in a little bit of duplicate setup for hardware like a serial console that is both a generic piece of code and that must be bootstrapped early.
, doesn't provide any means of doing initialization other than when PCI devices are initialized and doesn't give any control over *when* devices are initialized.
It is assumed the dependencies can be represented in the device tree. If you are higher up in the tree you are initialized first. And of devices in the same level of the device tree the order in the static tree pretty much rules.
chip_configure() allows devices to choose when in the boot sequence they want to perform some action, and allows multiple actions to occur for a single device.
It also provides no structure and it solves none of the hard problems. As for being able to do things in the boot sequence I have 6 methods to your 8. Plenty of opportunity to do weird things if need be.
I guess what I would like to avoid is representing what is essentially a motherboard dependent function call graph in a static device tree instead of just doing it straight forwardly in C.
What I don't see with chip_configure is it promoting any level of code reuse because what the calls do is not well defined. They are called in relationship to other code instead of being called to do something.
I'd be happy if the current scheme could provide this functionality, but I don't see any easy way to do it.
Hmm.
The fundamental problem I see is that Intel/AMD architectures do a lot more initialization prior to hardwaremain, so the functionality that I'm looking for is not really needed.
I agree that the current x86 ports do a substantial amount prior to hardwaremain, and so we don't have a few of your issues. That can easily be rectified.
Once you're in hardwaremain, basically all that's left to do is get PCI going.
Not at all.
This is not the case for PPC (and maybe other architectures.) The question is really: should linuxbios be Intel/AMD specific and required other architecture support grafted on, or should it be made general enough to work with any architecture. I guess I'm suggesting the latter.
I totally agree with the sentiment. And if you don't have very many devices that need their addresses programmed dynamically.
Eric
My example.
On the VT8231 south bridge, you need to set some bits very early in the game to make sure PCI devices are on or off, as needed by the motherboard.
So, in via/epia/auto.c, we have this:
static void enable_mainboard_devices(void) { device_t dev; /* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); #if 0 // This early setup switches IDE into compatibility mode before PCI gets // // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax // // movb $0x09, %dl // movb $0x00, %dl // PCI_WRITE_CONFIG_BYTE // #endif /* we do this here as in V2, we can not yet do raw operations * to pci! */ dev++; /* ICKY */ pci_write_config8(dev, 0x42, 0); }
OK, so I have some chip-specific stuff in the mainboard auto.c. Which means that other mainboards that use that chip have to use this code. First the authors of that code have to find this code. Chip-specific code like this should be in the southbridge chip code, not the mainboard code.
How do I want this to work?
Like this:
in via/vt8231/vt8231.c: static void southbridge_init(struct chip *chip, enum chip_pass pass) {
struct southbridge_via_vt8231_config *conf = (struct southbridge_via_vt8231_config *)chip->chip_info;
switch (pass) { case CONF_PASS_PRE_PCI: vt8231_pci_enable(conf); /* called BEFORE PCI scan */ break; }
}
I want that vt8231_pci_enable function called BEFORE any PCI config is done. But, as things stand, all the functions available in the C code depend on the dynamic device tree having been configure. But I need to call this function before that happens. The things that the function will do are determined in mainboard Config.lb, viz:
northbridge via/vt8601 "vt8601" southbridge via/vt8231 "vt8231" register "enable_usb" = "0" register "enable_native_ide" = "1" register "enable_com_ports" = "1" register "enable_keyboard" = "0" register "enable_nvram" = "1" end end
So, to make sure the PCI scan behave correctly and builds the dynamic tree correctly, I need to take actions BEFORE the PCI scan occurs. But the PCI functions provided to the C code only work AFTER the PCI scan occurs. Hence the problem.
This problem did not occur in v1.
I'd like the solution to be very simple ...
ron
ron minnich rminnich@lanl.gov writes:
So, to make sure the PCI scan behave correctly and builds the dynamic tree correctly, I need to take actions BEFORE the PCI scan occurs. But the PCI functions provided to the C code only work AFTER the PCI scan occurs. Hence the problem.
This problem did not occur in v1.
I'd like the solution to be very simple ...
I am grumpy because somehow in one of my merges the amd8111 piece of the code to do this got lost.
Basically you include the devices you care about in your static device tree and set an on/off flag to enable or disable them. And then you just need an appropriate enable method, for that device.
I will post the amd8111 version as soon as I get it recreated, and yes the code is pretty simple.
southbridge amd/amd8111 "amd8111" pci 0:0.0 on pci 0:1.0 on pci 0:1.1 on pci 0:1.2 on pci 0:1.3 on pci 0:1.5 on pci 0:1.6 off
end
Eric
On 10 Oct 2003, Eric W. Biederman wrote:
southbridge amd/amd8111 "amd8111" pci 0:0.0 on pci 0:1.0 on pci 0:1.1 on pci 0:1.2 on pci 0:1.3 on pci 0:1.5 on pci 0:1.6 off
end
BEAUTIFUL.
ron
ron minnich rminnich@lanl.gov writes:
On 10 Oct 2003, Eric W. Biederman wrote:
southbridge amd/amd8111 "amd8111" pci 0:0.0 on pci 0:1.0 on pci 0:1.1 on pci 0:1.2 on pci 0:1.3 on pci 0:1.5 on pci 0:1.6 off
end
BEAUTIFUL.
And baring bugs the enable function looks like:
void amd8111_enable(device_t dev) { device_t lpc_dev; unsigned index; uint16_t reg;
/* See if we are on the behind the amd8111 pci bridge */ if ((dev->bus->dev->vendor == PCI_VENDOR_ID_AMD) && (dev->bus->dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) { lpc_dev = dev_find_slot(dev->bus->dev->bus, dev->bus->path.pci.devfn + (1 << 3)); index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else { lpc_dev = dev_find_slot(dev->bus, dev->path.pci.devfn & ~7); index = dev->path.pci.devfn & 7; } if (index >= 16) { return; }
reg = pci_read_config16(lpc_dev, 0x48); reg &= ~(1 << index); if (dev->enable) { reg |= (1 << index); } pci_write_config16(lpc_dev, 0x48, reg); }
The one piece of this that I have not resolved yet is how to specify a device in the static device tree which has it's own internal pci bridge on it and devices behind that bridge.
The fun part here is that I can have multiple amd8111 with different pieces enabled.
I have a small theoretical problem if for some reason the device that controls the enables is does not precede the rest of the devices. But I will cross that bridge when I come to it.
Eric
ron minnich rminnich@lanl.gov writes:
So after the final tweaks the relevant bits look like:
southbridge amd/amd8111 "amd8111" link 0 pci 0:0.0 pci 0:1.0 on pci 0:1.1 on pci 0:1.2 on pci 0:1.3 on pci 0:1.5 off pci 0:1.6 off pci 1:0.0 on pci 1:0.1 on pci 1:0.2 on pci 1:1.0 off end
I have added a link option to chips specified in the static configuration file so I can remove it from the path of every device on the chip.
I have added a bus field to the pci configuration path. If it is 0 then it is an ordinary device on the same bus as the chip. If bus is > 0 then it specifies a previous device on the chip it is hanging off of. Bus 1 hangs off the first device bus 2 hangs off of the second device etc.
That allows me to fully handle the amd8111.
I have added an enable_dev method to the chip_control structure. This is in addition to the enable method for an individual device. Having two methods cleans up a lot of weird cases and it means you don't have to assign a device some operations just to disable it :)
I have also added a chip field to struct device so the original chip structure for a device can easily be found. Which should make getting at chip_info a snap.
The working example is now checked in under src/southbridge/amd8111/amd8111.c
.............
Skimming through your VIA example there is also the case of IDE and compatibility mode. As well as enabling/disabling individual IDE channels.
IDE compatibility mode pretty much should be handled by an appropriate read_resources routine.
As for enabling/disabling individual IDE channels I'm not quite sure yet. My gut feel says I need to put a bus/parent parameter back on all paths to devices inside a chip, and then have IDE path type so I can use the existing mechanisms. Alternatively I can just use the register mechanism, and have some special fields. Enabling/disabling IDE channels with the register mechanism looks like the easiest route at moment, so it should be tried first.
......
There is remaining work to be done for irq and other resource assignment. That code could really benefit from some generic code, as it is a general problem that affects all devices.
There is also remaining work to be done to export these things with the LinuxBIOS table.
At least everything else is working well enough that these are the big problems.
.....
Romcc now knows about switches and enums, and it's optimizers are no longer buggy. There are several constant cases, and data size cases it doesn't always get right. But the big thing for romcc is to teach it not to inline, which should get the code size down quite a bit. The infrastructure is in place for that, but that will have interesting effects on code when it is enabled so it needs to be introduced carefully.
Eric
ron minnich rminnich@lanl.gov writes:
On 8 Oct 2003, Eric W. Biederman wrote:
The current device resource assignment code should cope with static resource assignments, so hopefully it should be a matter of plugging hard codes into the device tree.
no, greg and I will be talking to you about this. There is a problem with that code, which I have alluded to, in that you can not (in the current system) do device assignments etc. before pci enumeration, and it is essential that you be able to do that.
Duh....
I had forgotten we do not have the ability to hard code resources assignments from the static tree in a generic way. I can do this in read_resources and friends and it has always been my intention to support it. Given that it does not yet exist it makes my suggestion a lot more work than I intended. Ultimately I still think it is a good idea though.
Ron without specific examples to talk through I cannot have this conversation. I believe think we have unspoken assumptions on how things should work, and without a mechanism to draw those assumptions out I don't see how we will make much progress.
The example with IDE does not have time constraints on when resources are assigned, so it does not illustrate to me what the problem you see is.
One of my assumptions is that the resource assignment code needs global information. So everything needs to wind up on the device tree.
Although looking at that code there is another issue. You are using dev_find_device in vt8231.c inappropriately. dev_find_device should be virtually unnecessary in the freebios2 tree. Except when you are very carefully using dev_find_device will fail to handle multiple instances of a device. This is a very bad example to set when doing things properly causes everything to work transparently.
legacy code. Has to get fixed.
Ok. We have some agreement.
Examples of proper usage welcomed.
The 8111 code does a fairly good job. The basic difference is when you fill in the proper method the dynamic code passes you the device so you don't need to go find it.
Although this actually points out a problem with the dynamic tree: it handles complex cases well, simple cases poorly.
Except for the very specific case of static resources which are not yet fully supported, I don't see that.
All I want to do is get into that device BEFORE pci enumeration and set some default values. You can't do that in the current scheme.
- The static device tree is BEFORE pci enumeration.
- read_resources can return a static value that the resource assignment code is not allowed to change.
So I do not see the specific problem you are seeing.
Eric
I picked up the values programmed to the IDE controller. At the first part (*1) it scans the base address registers and finally assigns the PCI I/O (*2), at this point this is no longer legacy compatible. And *3 is setting it to native mode.
In the vt8231.c, there is confusion about conf->enable_native_ide variable. As the name suggests, it should DISABLE legacy mode if this variable is 1. But for reg 0x42 it does the opposite.
I don't know how this thing works, but in mainboard/via/epia/Config.lb, it's set to 1. register "enable_native_ide" = "1"
Also I've noticed in V1, base address registers are explicitly cleared to zero in southbridge_fixup. I don't see this code moved to V2. Perhaps we should have a better way to do this..
$ grep 0x89 /tmp/epialog | grep '^Write' Write config 32 bus 0, devfn 0x89, reg 0x10, val 0xffffffff *1 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1f1 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x3f5 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x171 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x375 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0xcc01 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0xffffffff Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x24, val 0x0 Write config 32 bus 0, devfn 0x89, reg 0x10, val 0x1c51 *2 Write config 32 bus 0, devfn 0x89, reg 0x14, val 0x1c71 Write config 32 bus 0, devfn 0x89, reg 0x18, val 0x1c61 Write config 32 bus 0, devfn 0x89, reg 0x1c, val 0x1c81 Write config 32 bus 0, devfn 0x89, reg 0x20, val 0x1c41 Write config 8 bus 0, devfn 0x89, reg 0xd, val 0x40 Write config 8 bus 0, devfn 0x89, reg 0xc, val 0x10 Write config 16 bus 0, devfn 0x89, reg 0x4, val 0x81 Write config 8 bus 0, devfn 0x89, reg 0x42, val 0x9 Write config 8 bus 0, devfn 0x89, reg 0x40, val 0xb Write config 8 bus 0, devfn 0x89, reg 0x41, val 0xf2 Write config 8 bus 0, devfn 0x89, reg 0x43, val 0x35 Write config 8 bus 0, devfn 0x89, reg 0x44, val 0x18 Write config 8 bus 0, devfn 0x89, reg 0x45, val 0x1c Write config 8 bus 0, devfn 0x89, reg 0x9, val 0x8f *3 Write config 8 bus 0, devfn 0x89, reg 0x4, val 0x7 Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb Write config 8 bus 0, devfn 0x89, reg 0x3c, val 0xb
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