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Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

I will try the code and use normal scan. YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年12月4日 21:36 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: Tyan S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c > You put > /* Unmap all of the other pci busses */ > for(reg = 0xe0; reg <= 0xec; reg += 4) { > f1_write_config32(reg, 0); > } > > Why you need to clear that? After you clear that, I can not see the 8151 and > AGP in s2885. Hmm. This looks like a thinko. So right now the code says: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } return max; } And I think what I meant was: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); return max; } I don't have a clue why it works at all with clearing those registers after the pci bus scan. I wonder if that is the reason scan order matters because I don't clear those registers out first and things are dual mapped. Anyway my intention was to be very careful and to clear the HT chain mapping registers before we scanned them so we didn't have any old configurations getting in the way. Eric

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arima hdama success
by Craig C Forney 05 Dec '03

05 Dec '03

On Wed, 3 Dec 2003, Ron Minnich wrote > as of this morning, with Yh Lu's changes, arima hdama builds work fine. > >ron I'm not having the same success. I got the latest snapshot this evening, built for the arima hdama, and it fails the same way it has failed (hangs after printing out stuff below) for the last couple of months. Have Yh Lu's changes that fix the arima hdama been committed? If not, could someone point me to the changes that fix whatever this problem is? Thanks, Craig Forney Opus Innovations LLC LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 starting... setting up resource map.... AMD8111 southbridge is connected to HT link 00000000 setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling SMP settings setup_remote_node setup_remote_done Renaming current temp node to 00000001 done. Enabling routing table for node 00000001 done. 00000002 nodes initialized. detect_mp_capabilities: 00000002 coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 166Mhz Interleaved RAM: 0x00100000 KB Ram2.01 Enabling dual channel memory disabling dimm00 disabling dimm01 disabling dimm00 disabling dimm01 200Mhz disabling dimm00 disabling dimm01 RAM: 0x00100000 KB Ram3 ECC enabled ECC enabled Initializing memory: done Clearing memory: addr 00000000-0000003f ----------------done Initializing memory: done Clearing memory: addr 00000040-0000003f done Ram4 PCI: 00:01.00 00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 00 2c 00 00 50: 00 00 02 00 00 00 04 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 00 03 00 0e 00 ff ff 02 00 ff ff b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 00 c0: 08 00 41 00 20 00 11 00 20 00 00 00 22 00 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 08 0c 00 08 08 0d 00 0f 0f 13 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.01 00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 ... PCI info deleted for brevity ... 80: 33 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 80 0a 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: a3 88 1e 5a 02 00 00 00 8c 5b b7 d6 72 9f e7 ef c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 04 67 05 44 e4 ae 6b 16 9e 4f 10 40 c5 1b cc 44 e0: d9 c6 0a 24 48 04 5c 10 38 6c 03 48 86 74 2e 26 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:18.03 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 40 00 be fc 07 77 73 80 7b 46 50: 08 a5 f7 0b 88 00 00 00 16 16 16 00 00 04 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 02 00 00 00 70 0f 00 00 00 83 06 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 01 00 00 e0 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 20 10 00 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: NSC 87360 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [ffff/ffff] enabled PCI: 00:19.1 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 00:19.1 No device operations

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Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c You put /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } Why you need to clear that? After you clear that, I can not see the 8151 and AGP in s2885. PS: I have reversed the scan sequence to make sure HT scan 8111 at first and then 8151. Regards Yinghai Lu

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Level 2 cache activation code?
by Svante Signell 04 Dec '03

04 Dec '03

Hello, I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino) 300@450MHz with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2 1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable). The problem is that the latest MSI BIOS (v2.0) for the mobo does not support Coppermine/Tualatin processors. The single GNU/Linux kernels boot without problems but _extremely_ slowly, at least with a speed reduction by a factor 10. hdparm -tT gives around 20/2 compared with 250/25 with the Mendocino CPU(s). For example uncompressing the kernel takes minute(s) compared to seconds. After some trials and web searching I suspect that the problem is with the level 2 cache not activated by the BIOS. I see the you have code in the linuxbios for activating caches. i) Does this code work for 440BX motherboards? ii) Is it possible to extract this code and try out after the kernel has booted (slowly), to verify my assumption? iii) Is there some other tool available for cache activation? iv) One interesting continuation would be to try to replace the MSI (AMI) BIOS with linuxbios, but as a first step I think this would be a little risky. Any ideas? Thanks, Svante

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Doubt with Diskonchip millennium?
by Devi Priya 04 Dec '03

04 Dec '03

Hi, In the application note (AP044) from Msystems diskonchip it is given as: "The DiskOnChip Millennium is mapped into an 8KB memory window in the host platforms memory map. This 8KB window consists of four 2KB windows." Why is this mapping done? Is this done for all the DiskOnChip Millennium? The steps for BIOS is summarised as 1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the Reset Vector from the Boot-Block area, fetches the Boot Code stored there, and starts to execute the code. 2. Boot Code runs the first part of BIOS, initializing the basic hardware functionality. 3. Boot Codes loads the rest of the BIOS from the flash memory to the DRAM, and transfer control (jumps) there. 4. Chip Select of DiskOnChip Millennium is remapped from Reset Vector to BIOS expansion area. 5. CPU executes the rest of the BIOS code, including ROM expansion devices (among them, the DiskOnChip Millennium itself). 6. CPU calls OS bootstrap loader (INT19). 7. OS is loaded, and recognizes the DiskOnChip Millennium as the boot device. 8. OS loads the application code from the DiskOnChip Millennium and executes it. 9. Application software uses DiskOnChip Millennium exactly as if it were using a regular hard disk. In step 4 why is this remapping done _________________________________________________________________ Shop online for kids toys by age group, price range, and toy category at MSN Shopping. No waiting for a clerk to help you! http://shopping.msn.com

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Re: Diskonchip ipl code for sc1200?
by Devi Priya 04 Dec '03

04 Dec '03

Hi, Thanks for ur suggestion. Should I write both ipl code for the chipset and the DOCM? Should I also write the SPL code for chipset and DOCM? Can I use the ipl and spl code given with the xpressloader BootLoader Development Kit? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Diskonchip ipl code for sc1200? >Date: Wed, 3 Dec 2003 07:34:03 -0700 (MST) > >On Wed, 3 Dec 2003, Devi Priya wrote: > > > I could not find any ipl code for sc1200 (nano mainboard). Which >should I > > mention in the config file for docipl? Please give me suggestion. > >you'll have to write it. > >ron > >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios _________________________________________________________________ It is Ms World time! Send in your wishes to Ami Vashi. http://server1.msn.co.in/sp03/Missworld2003/ Help her bring home the crown!

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Filesystem for doc?
by Devi Priya 03 Dec '03

03 Dec '03

Hi, Which filesystem should I use for diskonchip? Should I use ths True FFS or can I use the NFTL? _________________________________________________________________ Love shopping online? Get this e credit card. http://server1.msn.co.in/features/amex/ Save cost, add value!

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Re: Tyan S2885
by YhLu 03 Dec '03

03 Dec '03

Output -----邮件原件----- 发件人: YhLu 发送时间: 2003年12月3日 18:34 收件人: YhLu; ebiederman(a)lnxi.com 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Tyan S2885 Eric, I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c You put /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } Why you need to clear that? After you clear that, I can not see the 8151 and AGP in s2885. PS: I have reversed the scan sequence to make sure HT scan 8111 at first and then 8151. Regards Yinghai Lu

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irq tables generation
by Stefan Reinauer 03 Dec '03

03 Dec '03

Hi, * ron minnich <rminnich(a)lanl.gov> [031202 00:28]: > > {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0}, > > > pci_assign_irqs(2, 0x5, dualenetbIrq);'' > > in addition i had to play with the irq lists. > > eek. You know that this is exactly the wrong way to do this and why, I > assume. But it works, so keep it for now. But this will never go into the > CVS. Do we agree that interrupts should be _unassigned_ during firmware execution and set by the OS only? Another way of handling this might be to set some default values and allow the OS to reconfigure those. A PIRQ-Table has to contain * one entry for each PCI device that needs an interrupt * one entry for each peer bus to be visible. It seems we know these parameters in-system already and can generate a valid table assuming some fixed parameters (cycling interrupts a la {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}} and a fixed mask of 0xdeb8. > irq_table.c is for linux, it tells linux how the irqs are wired up. In an > ideal world, linuxbios would hand the irq table to linux or plan9 or *bsd > and those OSes would do everything correctly. In our world, each of these > OSes get it wrong often enough that we have to now assign it directly. I > had hoped to avoid IRQ assignment in linuxbios but it seems that we have > no choice -- too many busted hardware/OS bits out there. Not to forget the mptable - that contains additional information on which busses are available - information that Linux obviously don't like to read from there but from the irq table. Stefan -- Stefan Reinauer, SUSE LINUX AG Teamleader Architecture Development

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Re: config -> default
by Greg Watson 03 Dec '03

03 Dec '03

Stefan, Which builds are broken? I thought I checked all configurations built after the change (apart from the VIA which Ron was working on.) and modified any that had problems. My hope was that this change would make the use of options more logical and consistent. The intention is that parts set default values for any options that they require or are specific to the part. Then when all the parts are put together in a target configuration file, these default values can be overridden for the specific build. I was also toying with the idea of allowing some options to be read-only, which I think would address your concern. Apologies for breaking things. I try to build all targets after any change like this to make sure things are still working. Greg At 4:16 PM +0100 11/6/03, Stefan Reinauer wrote: >Hi, > >most of the builds are broken again since "config" in the mainboard >config file now has to be renamed to "default". On the one hand I see >the reason for most of these changes, even though I am not sure if >we want to suggest that some stuff can be overridden in the target >config file, like: > >-option CONFIG_IOAPIC=1 >+default CONFIG_IOAPIC=1 > >Can those changing elementary stuff like this that breaks all builds try >to apply some regexps on the Config files so that other builds don't >break? Getting further is somewhat hard currently since the code almost >instantly breaks after the last fixes are checked in.. > >Stefan > >-- > Stefan Reinauer, SUSE LINUX AG >Teamleader Architecture Development >_______________________________________________ >Linuxbios mailing list >Linuxbios(a)clustermatic.org >http://www.clustermatic.org/mailman/listinfo/linuxbios

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