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Re: for all k8 builders
by YhLu 08 Dec '03

08 Dec '03

I will check the code.

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for all k8 builders
by ron minnich 08 Dec '03

08 Dec '03

your builds are broken today due to the missing amdk8.h file in src/northbridge/amd/amdk8. Do an update; I just added it. ron

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Hardware Help with diskonchip?
by Devi Priya 08 Dec '03

08 Dec '03

Hi, In the application note (AP044) from Msystems it is given as: "The DiskOnChip Millennium is mapped into an 8KB memory window in the host platforms memory map. This 8KB window consists of four 2KB windows." Why is this mapping done? Is this mapping done in hardware? I use diskonchip millennium (8MByte MD2800). Then shouldn't the entire 8MB shall be mapped in hardware to the physical address space? The steps for BIOS is summarised as 1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the Reset Vector from the Boot-Block area, fetches the Boot Code stored there, and starts to execute the code. 2. Boot Code runs the first part of BIOS, initializing the basic hardware functionality. 3. Boot Codes loads the rest of the BIOS from the flash memory to the DRAM, and transfer control (jumps) there. 4. Chip Select of DiskOnChip Millennium is remapped from Reset Vector to BIOS expansion area. 5. CPU executes the rest of the BIOS code, including ROM expansion devices (among them, the DiskOnChip Millennium itself). 6. CPU calls OS bootstrap loader (INT19). 7. OS is loaded, and recognizes the DiskOnChip Millennium as the boot device. 8. OS loads the application code from the DiskOnChip Millennium and executes it. 9. Application software uses DiskOnChip Millennium exactly as if it were using a regular hard disk. In step 4 why is this remapping done? Is this mapping done in hardware? In my setup, the diskonchip is mapped in hardware to the higher order address (0xFFFFFFFF-0xFF800000). SDRAM mapped to lower address (0x00000000-0x1FFFFFF). What else modification do i require in HARDWARE to use diskonchip millennium? _________________________________________________________________ Add zing to Hotmail. Get FREE newsletters. http://server1.msn.co.in/features/general/Newsletters/index.asp Subscribe now!

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Will this work ??
by Stefan 07 Dec '03

07 Dec '03

Hi there, I've a Gigabyte GA-7NNXP with nForce II Chipset, and a BIOS with a size of 512 KB. Will I be able to get a open source "bios" work on that mainboard ? thx for your helping!!

5 4

Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

S2885 updated to 1.1.5 Only reset once.

1 0

Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, Great, it works. Even normal scan it can find out 8151. But the bus number is funny, I may need to update bus number mptable.c and irq_table.c and reset.c I wonder if 8151 on CPU 1 and 8131/8111 on CPU0. is the amdk8_scan_root_bus called two times? If so, you may keep the > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > if((value>>24)>max) > f1_write_config32(reg, 0); > } Regards YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年12月5日 15:26 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: Tyan S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I change amdk8_scan_root_bus to: > > unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) > { > unsigned reg; > uint32_t value; > /* Unmap all of the other pci busses */ > printk_debug("\nbefore pci_scan_bus\n"); > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > if((value>>24)>max) > f1_write_config32(reg, 0); > } > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > } > > max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); > > printk_debug("after pci_scan_bus\n"); > for(reg = 0xe0; reg <= 0xec; reg += 4) { > value = f1_read_config32(reg); > printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", > reg,value,max); > } > > return max; > } > > I think as least you only need to clear the regs that contain bigger bus > number than the next bus for scanning. > > The result will be in the end. > > The problems: > 1. It can not access 8151 on CPU link0 and so can not scan it > 2. The HT scan seems can not figure out and set the link and read/write > enable bit in e0. It set the e0 to 0x05050000 Doh. The Opteron is too forgiving when you only have one link. It makes this kind of debugging a pain. What I am doing should not work but it does in that case... My apologies, for missing this. In amdk8_scan_chains() there is the snippet: config_busses &= 0x0000ffff; config_busses |= ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); Which is the offending piece of code. It neither sets the link that we are supposed to go out, nor does it set the r/w enable bits. Ouch. It only works if those registers are pre programmed. So I think this should be: config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | (( link & 3 ) << 8) | ((dev->link[link].secondary) << 16) | ((dev->link[link].subordinate) << 24); f1_write_config32(config_reg, config_busses); Eric

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Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, I change amdk8_scan_root_bus to: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; uint32_t value; /* Unmap all of the other pci busses */ printk_debug("\nbefore pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); if((value>>24)>max) f1_write_config32(reg, 0); } for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); printk_debug("after pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } return max; } I think as least you only need to clear the regs that contain bigger bus number than the next bus for scanning. The result will be in the end. The problems: 1. It can not access 8151 on CPU link0 and so can not scan it 2. The HT scan seems can not figure out and set the link and read/write enable bit in e0. It set the e0 to 0x05050000 Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 14:29:03 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 amdk8_scan_root_bus e0 = 0 max = 0 amdk8_scan_root_bus e4 = 0 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 Missing static device: PCI: 05:00.0 HyperT reset not needed PCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:01.0 No device operations PCI: pci_scan_bus returning with max=05 Hyper transport scan link: 0 new max: 5 Hypertransport scan link done amdk8_scan_chains max: 5 done amdk8_scan_chains max: 5 starting... amdk8_scan_chains max: 5 done PCI: pci_scan_bus returning with max=05 after pci_scan_bus amdk8_scan_root_bus e0 = 5050000 max = 5 amdk8_scan_root_bus e4 = 0 max = 5 amdk8_scan_root_bus e8 = 0 max = 5 amdk8_scan_root_bus ec = 0 max = 5 done Allocating resources... PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 80 <- [0xfec00000 - 0xfebfffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xfe900000 - 0xfebfffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:00.0 missing set_resources PCI: 05:01.0 missing set_resources ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xfe900000 - 0xfe9fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xfe900000 - 0xfe90ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xfeb00000 - 0xfeb00fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xfeb00000 - 0xfeafffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xfeb00000 - 0xfeafffff] bus 3 mem PCI: 01:02.1 10 <- [0xfeb01000 - 0xfeb01fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xfeb00000 - 0xfeafffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xfea00000 - 0xfeafffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xfea04000 - 0xfea04fff] mem PCI: 04:00.1 10 <- [0xfea05000 - 0xfea05fff] mem PCI: 04:00.2 10 <- [0xfea08000 - 0xfea080ff] mem PCI: 04:00.2 14 <- [0xfea09000 - 0xfea0901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xfea07000 - 0xfea073ff] mem PCI: 04:0c.0 10 <- [0xfea06000 - 0xfea067ff] mem PCI: 04:0c.0 14 <- [0xfea00000 - 0xfea03fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:00.0 missing enable_resources PCI: 05:01.0 missing enable_resources PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu

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Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, If don't clear the regs, the result will be: Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 15:05:21 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 HyperT reset needed PCI: pci_scan_bus for bus 5 PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled PCI: pci_scan_bus for bus 6 PCI: 06:00.0 [10de/0322] enabled PCI: pci_scan_bus returning with max=06 PCI: pci_scan_bus returning with max=06 Hyper transport scan link: 0 new max: 6 Hypertransport scan link done amdk8_scan_chains max: 6 done amdk8_scan_chains max: 6 starting... amdk8_scan_chains max: 6 done PCI: pci_scan_bus returning with max=06 after pci_scan_bus amdk8_scan_root_bus e0 = 4010203 max = 6 amdk8_scan_root_bus e4 = 6050003 max = 6 amdk8_scan_root_bus e8 = 0 max = 6 amdk8_scan_root_bus ec = 0 max = 6 done Allocating resources... PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 80 <- [0xe0000000 - 0xf8ffffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xf9000000 - 0xf92fffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 05:02.0 1c <- [0x00003000 - 0x00002fff] bus 6 io PCI: 05:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 6 prefmem PCI: 05:02.0 20 <- [0xf8000000 - 0xf8ffffff] bus 6 mem ASSIGN RESOURCES, bus 6 PCI: 06:00.0 10 <- [0xf8000000 - 0xf8ffffff] mem PCI: 06:00.0 14 <- [0xf0000000 - 0xf7ffffff] prefmem ASSIGNED RESOURCES, bus 6 ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xf9200000 - 0xf91fffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xf9000000 - 0xf90fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xf9000000 - 0xf900ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xf9200000 - 0xf9200fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xf9200000 - 0xf91fffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xf9200000 - 0xf91fffff] bus 3 mem PCI: 01:02.1 10 <- [0xf9201000 - 0xf9201fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xf9200000 - 0xf91fffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xf9100000 - 0xf91fffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xf9104000 - 0xf9104fff] mem PCI: 04:00.1 10 <- [0xf9105000 - 0xf9105fff] mem PCI: 04:00.2 10 <- [0xf9108000 - 0xf91080ff] mem PCI: 04:00.2 14 <- [0xf9109000 - 0xf910901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xf9107000 - 0xf91073ff] mem PCI: 04:0c.0 10 <- [0xf9106000 - 0xf91067ff] mem PCI: 04:0c.0 14 <- [0xf9100000 - 0xf9103fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:01.0 cmd <- 06 PCI: 05:02.0 bridge ctrl <- 003e PCI: 05:02.0 cmd <- 07 PCI: 06:00.0 cmd <- 03 PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu

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Update to pirq_routing
by Jordan Archer 05 Dec '03

05 Dec '03

The following is the diff for a change I made. I think the HAVE_PIRQ_TABLE is always defined and this allowed me to turn off the existence of a routing table. Jordan RCS file: /cvsroot/freebios/freebios2/src/arch/i386/include/arch/pirq_routing.h,v retrieving revision 1.1 diff -r1.1 pirq_routing.h 42c42,43 < #if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) --- > //#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) > #if defined(DEBUG) && HAVE_PIRQ_TABLE // JORDAN: This needs to be dependent on value, not existence. 48c49,50 < #if defined(HAVE_PIRQ_TABLE) --- > //#if defined(HAVE_PIRQ_TABLE) > #if HAVE_PIRQ_TABLE // JORDAN: This needs to be dependent on value, not Index: romcc_io.h ===================================================================

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Re: Tyan S4880
by YhLu 05 Dec '03

05 Dec '03

Ron, Please check in the Tyan s2850/2880/2881/2882/4880 updates into the CVS Tree. 1. northbridge/amd/amdk8/raminit.h: change uint8_t to uint16_t 2. southbridge/amd/amd8111/amd8111_early_smbus.c: update smbus_write_byte 3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable PCI-X MASTER Mode. 4. other in /src/mainboard/tyan/ and /targets/tyan Stefan, With update 1 and 2, you can get ride of FAKE_SPD_ROM. You need to change some lines in auto.c for quartet. 1. I2C HUB address: 0x30 --> 0x18, 2. RC0-> (1<<1)<<8, RC1-> (1<<2)<<8, RC2-> (1<<3)<<8, RC3-> (1<<4)<<8. Regards YH.

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