coreboot

coreboot@coreboot.org

5 participants
39567 discussions

Re: ep405pc
by Greg Watson 04 Oct '03

04 Oct '03

Update on the ep405pc: getting close! Fixed hardwired address and byte ordering issue with the low-level PIC routines. Now I see: LinuxBIOS-1.1.4 Sat Oct 4 16:54:15 MDT 2003 rebooting... Finding PCI configuration type. Enumerating: Winbond W83C553 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1014/0156] enabled PCI: 00:09.0 [10ad/0565] enabled PCI: 00:0e.0 [1045/c861] enabled PCI: pci_scan_bus returning with max=00 done dev_configure: Allocating resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 14 <- [0xfe9ff000 - 0xfebfefff] prefmem PCI: 00:0e.0 10 <- [0xfebff000 - 0xfebfffff] mem ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:00.0 cmd <- 06 PCI: 00:09.0 cmd <- 07 PCI: 00:0e.0 cmd <- 02 done. Initializing devices... Devices initialized Found W83C553F controller Error: Cannot find W83C553F function 1 device No memory size information! Cheers, Greg

1 0

V2 EPIA: success
by ron minnich 03 Oct '03

03 Oct '03

Linux is now up. Tweak this, tweak that in southbridge and at some point it works. Looks like we needed some ISA config to make it go. So V2 is up on the EPIA. Now if we can all come to closure on the config tool we'll be getting there :-) This afternoon I will try to get the memory system to be sane. Wow, this is fun, these little EPIAs are great cluster nodes. Small box, wrapped in steel so I can't break anything, powered by a wall wart. I love 'em. ron

2 3

one other EPIA question
by ron minnich 03 Oct '03

03 Oct '03

is there a register somewhere we can read to figure out FSB clock rate (66 vs 133). This is important for timing. ron

2 1

V2 VIA EPIA -- SPD.
by ron minnich 02 Oct '03

02 Oct '03

OK, the first SPD work is in. Ram size is now set from SPD. The next line of attack are the MA registers. The code is walking a tight line between code space size and register allocation; see northbridge/via/vt8601/raminit.c for some details. These old pentiums are tight on registers! That said, doing this in C is even better than having an ICE. ron

2 2

Re: V2 VIA EPIA
by YhLu 02 Oct '03

02 Oct '03

Any plan on moving other to V2? Intel chipset? Serverworks chipset? Sis chipset? Other?? Regards YH -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2003年10月2日 16:37 收件人: linuxbios(a)clustermatic.org 主题: V2 VIA EPIA OK, I'm done for a while. This thing is working well enough, I have some other things to do, and I think it is an ok example (criticism is welcome and appreciated, as long as it comes with suggestions for how to improve things). I did put some timing test and control in raminit.c, and it computes what looks like OK timing numbers, but if I use those numbers the machine locks up. You can see the code if interested in CVS. That's what i remember about this north bridge -- it's tricky to get it right. I think we should just leave it at the most conservative timings for now. I would like to know if there are other SPD parameters we ought to try to compute besides MA. Size was an important one to figure out, and it works now, but there are others we might want. Note that right now, due to space limitations, only the first two DRAM slots are getting configured. Please let me know if this is an issue for anyone. ron _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

2 1

V2 VIA EPIA
by ron minnich 02 Oct '03

02 Oct '03

OK, I'm done for a while. This thing is working well enough, I have some other things to do, and I think it is an ok example (criticism is welcome and appreciated, as long as it comes with suggestions for how to improve things). I did put some timing test and control in raminit.c, and it computes what looks like OK timing numbers, but if I use those numbers the machine locks up. You can see the code if interested in CVS. That's what i remember about this north bridge -- it's tricky to get it right. I think we should just leave it at the most conservative timings for now. I would like to know if there are other SPD parameters we ought to try to compute besides MA. Size was an important one to figure out, and it works now, but there are others we might want. Note that right now, due to space limitations, only the first two DRAM slots are getting configured. Please let me know if this is an issue for anyone. ron

1 0

Memory speed
by ron minnich 02 Oct '03

02 Oct '03

Is there a handy-dandy memory timing too out there? I am used to using lmbench but I'd like something a bit smaller and simpler. Thanks ron

1 0

V2 VIA EPIA testing
by ron minnich 02 Oct '03

02 Oct '03

I just tested the node with different memory dimms of different size and they're fine. We're going to be glad we made it to V2, and that we finally did SPD for this platform. ron

1 0

Re: V1 SiS 630 VGA problem - any advice?...
by SONE Takeshi 02 Oct '03

02 Oct '03

On Thu, Oct 02, 2003 at 10:46:32AM +0100, Lee Weekes wrote: > INSTALL REAL-MODE IDT > DO THE VGA BIOS > PCI_CLASS_DISPLAY_VGA: 300 > found VGA: vid=1039, did=6300 > 0x55 0xaa 0x60 0xe9 0x5f 0x2 0x32 0x2e 0x30 0x33 0x2e 0x30 0x32 0x20 > 0x2d 0x31 > biosint: # 0x1a, eax 0xb102 ebx 0xeb21 ecx 0x16300 edx 0x1039 > biosint: ebp 0x14c64 esp 0xfce edi 0x10c8c esi 0x80000 > biosint: ip 0x762 cs 0xeb21 flags 0x46 > 0xb102: return 0x100 > biosint: # 0x15, eax 0xf401 ebx 0x105 ecx 0x10100 edx 0x1039 > biosint: ebp 0x14c64 esp 0xfce edi 0x10c8c esi 0x80000 > biosint: ip 0x76b cs 0xeb21 flags 0x46 > biosint: Unsupport int #0x15 > biosint: # 0x7, eax 0x300001f ebx 0x0 ecx 0x0 edx 0x3c4 > biosint: ebp 0x10fae esp 0xfce edi 0x1379c esi 0x800eb > biosint: ip 0x5b4 cs 0xeb21 flags 0x216 > biosint: Unsupport int #0x7 > // <-- Int7 call looks out of place? > biosint: # 0x > > At the point it freezes the last post code visible is 11 (was EC just > before and I can't see 11 anywhere in the linuxbios tree) and I also get > 1 continuous beep sounded from the buzzer which sounds worrying. Looks like you don't use the latest idt.c and vgabios.c. Try these files from http://snapshots.linuxbios.org/ -- Takeshi

1 0

Patch for V2 new config
by Mark Wilkinson 02 Oct '03

02 Oct '03

Hi Ron, I started looking at building the Via/Epia with the v2, and noticed that your last snapshot said that the mainboard Config.lb should set the ROM_SIZE to 265K. Here's a little patch that lets the config python use 'default OPTION value' tag in the Mainboard Config.lb overriding the value set in config/Optins.lb (which has ROM_SIZE set to NONE) or should the command be 'default OPTION=<value>' in which case, alter the line for 'rule default<<C>>: ...' to read rule default<<C>>: DEFAULT ID EQ value {{ if(C): mbdefault(ID,value) }} Regards Mark Wilkinson. PS. Hope to burn a V2 epia bios tomorrow morning and test !!

5 16

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot