coreboot

coreboot@coreboot.org

39717 discussions

Re: [LinuxBIOS] [Etherboot-developers] Universal boot disk etc...
by Lu, Yinghai 03 Jan '06

03 Jan '06

Memory limitation? We can set _RAMBASE to 1M above. I wonder if Etherboot can put the code in RAM above 1M... Otherway for universal boot: Tiny kernel with all driver need ---- ramdisk or initramfs to kexec other kernel.... YH

1 0

[LinuxBIOS] Fwd: [Linux-fbdev-devel] gx1fb: (try to) play nicer with various BIOSes
by Richard Smith 03 Jan '06

03 Jan '06

This came across the linux-fb-dev list. I know some people are using the GX1 so I'm posting it here. ---------- Forwarded message ---------- From: David Vrabel <dvrabel(a)arcom.com> Date: Jan 3, 2006 10:18 AM Subject: [Linux-fbdev-devel] gx1fb: (try to) play nicer with various BIOSes To: linux-fbdev-devel list <linux-fbdev-devel(a)lists.sourceforge.net> Hi, Seems that the CS5530A chip used in Geode GX1 systems has some crazy feature that causes SMI traps when accessing the PCI configuration space of the video device. Various GX1 BIOSes seem to use this 'feature' to hide the real BARs of the device. This patch disables these traps (in an early PCI fixup) so that Linux sees the real, physical BARs and not the virtual ones provided by the BIOS. This should allow the GX1 framebuffer driver to work on more systems that have different BIOSes as the driver no longer guesses at what the virtual BARs mean. I'm not entirely sure it the correct solution as I can neither test regular VGA console nor the X's 'cyrix' video driver so there might be some breakage there -- probably best to get some more testers before applying it. David Vrabel -- David Vrabel, Design Engineer Arcom, Clifton Road Tel: +44 (0)1223 411200 ext. 3233 Cambridge CB1 7EA, UK Web: http://www.arcom.com/ Index: linux-2.6-working/arch/i386/pci/fixup.c =================================================================== --- linux-2.6-working.orig/arch/i386/pci/fixup.c 2006-01-03 08:46:51.000000000 +0000 +++ linux-2.6-working/arch/i386/pci/fixup.c 2006-01-03 15:59:54.000000000 +0000 @@ -442,3 +442,19 @@ } DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, pci_post_fixup_toshiba_ohci1394); + + +/* + * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device + * configuration space. + */ +static void __devinit pci_early_fixup_cyrix_5530(struct pci_dev *dev) +{ + u8 r; + /* clear 'F4 Video Configuration Trap' bit */ + pci_read_config_byte(dev, 0x42, &r); + r &= 0xfd; + pci_write_config_byte(dev, 0x42, r); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, + pci_early_fixup_cyrix_5530); Index: linux-2.6-working/drivers/video/geode/gx1fb_core.c =================================================================== --- linux-2.6-working.orig/drivers/video/geode/gx1fb_core.c 2006-01-03 08:46:54.000000000 +0000 +++ linux-2.6-working/drivers/video/geode/gx1fb_core.c 2006-01-03 16:00:43.000000000 +0000 @@ -215,11 +215,11 @@ if (ret < 0) return ret; - ret = pci_request_region(dev, 1, "gx1fb (video)"); + ret = pci_request_region(dev, 0, "gx1fb (video)"); if (ret < 0) return ret; - par->vid_regs = ioremap(pci_resource_start(dev, 1), - pci_resource_len(dev, 1)); + par->vid_regs = ioremap(pci_resource_start(dev, 0), + pci_resource_len(dev, 0)); if (!par->vid_regs) return -ENOMEM; @@ -229,12 +229,9 @@ if (!par->dc_regs) return -ENOMEM; - ret = pci_request_region(dev, 0, "gx1fb (frame buffer)"); - if (ret < 0 ) - return -EBUSY; if ((fb_len = gx1_frame_buffer_size()) < 0) return -ENOMEM; - info->fix.smem_start = pci_resource_start(dev, 0); + info->fix.smem_start = gx_base + 0x800000; info->fix.smem_len = fb_len; info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); if (!info->screen_base) -- Richard A. Smith

1 0

[LinuxBIOS] Is my Geode GX1 support?
by unknown user 02 Jan '06

02 Jan '06

CPU: National Semiconductor Geode GX1 266Mhz Mainboard Chipset: National Semiconductor CS5530A I dunno what chipset use in SuperIO chipset. Sorry. root@xxxx:~# lspci -vvv 0000:00:00.0 Host bridge: Cyrix Corporation PCI Master Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 0000:00:0e.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B+ Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (63750ns min, 63750ns max) Interrupt: pin A routed to IRQ 15 Region 0: I/O ports at f800 [size=256] Region 1: Memory at fedff000 (32-bit, non-prefetchable) [size=4K] Expansion ROM at <unassigned> [disabled] [size=64K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 0000:00:12.0 ISA bridge: Cyrix Corporation 5530 Legacy [Kahlua] (rev 30) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, Cache Line Size: 0x04 (16 bytes) 0000:00:12.1 Bridge: Cyrix Corporation 5530 SMI [Kahlua] Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40012000 (32-bit, non-prefetchable) [size=256] 0000:00:12.2 IDE interface: Cyrix Corporation 5530 IDE [Kahlua] (prog-if 80 [Master]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 4: I/O ports at fc00 [size=16] 0000:00:12.3 Multimedia audio controller: Cyrix Corporation 5530 Audio [Kahlua] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Region 0: Memory at 40011000 (32-bit, non-prefetchable) [size=128] 0000:00:12.4 VGA compatible controller: Cyrix Corporation 5530 Video [Kahlua] (prog-if 00 [VGA]) Subsystem: Cyrix Corporation: Unknown device 0001 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at 40800000 (32-bit, non-prefetchable) [size=8M] 0000:00:13.0 USB Controller: Compaq Computer Corporation ZFMicro Chipset USB (rev 06) (prog-if 10 [OHCI]) Subsystem: Compaq Computer Corporation ZFMicro Chipset USB Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 11 Region 0: Memory at fedfe000 (32-bit, non-prefetchable) [size=4K] here is more infomation http://kil13r.info/hardware.html (crowled by lshw util) sorry for my poor english. - Chae Jong-bin

2 2

[LinuxBIOS] I855 raminit.c hang up
by Daniel Toussaint 30 Dec '05

30 Dec '05

Hi, I have a board with an I852/ICH4 chipset (lspci output attached). i am trying to get something up and running based on the digitallogic/adl855pc board. During memory initialization , in northbridge/intel/i855pm/raminit.c the system hangs up in do_ram_command() when executing read32(dword) , where dword is 0x0000 Ram Enable 3 P:10 R:11 R:00000000 Is this a known problem ? Any tips ? If not, I will just keep on trying to find out what is wrong, but given my limited knowledge/experience with initialization of memory controllers, it may take me a long time. Thanks, ------> lspci <---------- 0000:00:00.0 Host bridge: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 0000:00:00.1 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 0000:00:00.3 System peripheral: Intel Corporation 82852/82855 GM/GME/PM/GMV Processor to I/O Controller (rev 02) 0000:00:02.0 VGA compatible controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 0000:00:02.1 Display controller: Intel Corporation 82852/855GM Integrated Graphics Device (rev 02) 0000:00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02) 0000:00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02) 0000:00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02) 0000:00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02) 0000:00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) 0000:00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02) 0000:00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02) 0000:00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02) 0000:00:1f.5 Multimedia audio controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller (rev 02) 0000:01:08.0 Ethernet controller: Intel Corporation 82801DB PRO/100 VE (CNR) Ethernet Controller (rev 82)

2 1

[LinuxBIOS] GRUB vs LinuxBIOS question
by Svante Signell 29 Dec '05

29 Dec '05

Hi, I'm currently reading the mailing list archives on GRUB V2 and LinuxBIOS development. Can somebody please enlighten me on the interfaces between the two development projects. In an ideal world one should have open source, or preferably free software solutions, for the BIOS code too. Are there any overlaps in functionality that could be synchronised between the groups? Is anything tutorial-like written explaining the different functionality of the (Linux)BIOS (CPU, memory, peripheral initialisation, etc) and GRUB (kernel loading, transfer of control to kernel etc). Thanks, -- Svante Signell <svante.signell(a)telia.com>

3 2

Re: [LinuxBIOS] Gigabyte's DualBios and recovery from a botched Linuxbios flash?
by David Hendricks 28 Dec '05

28 Dec '05

Doesn't look like it: http://www.ioss.com.tw/web/English/RD1BIOSSavior/SelectionSheet.html Does your mainboard actually come with an 8mb chip? Looks like you might need to settle for 4mb if you require a BIOS Savior --David On Wed, 28 Dec 2005 04:43:17 -0600 "Young, Jeff" <Jeff.Young(a)gd-ais.com> wrote: > > I can't seem to find a BIOS Savior for an 8mb chip. Does it exist? > > Thanks, > Jeff Young

2 1

Re: [LinuxBIOS] Gigabyte's DualBios and recovery from a botched Linuxbiosflash?
by sales＠bradbrown.com 28 Dec '05

28 Dec '05

I think I'll go with the replacement ZIF socket as described by Bari. I had no idea it was that easy to remove a TSOP device, so that approach never occured to me. I would consider another motherboard with socketed bios, but given the price constraints I'm forced to work in (sub $100, NForce4), it seems that most boards in that range have TSOP bioses. Also, I wanted to re-read the FAQ portions regarding flashing, but keep receiving a "A database query syntax error has occurred" error when I click on the FAQ link on the main LinuxBios.org website. I could not find a contact email (the help link was broken as well), so could one of you relay a "FAQ is down" message to the website maintainer? Thanks, Brad Brown Bari Ari wrote: >If there is enough room around the tsop flash device on the mainboard, >the flash device may be replaced by a ZIF tsop socket. Such as one by: > >http://www.emulation.com/catalog/off-the-shelf_solutions/sockets/tsop/ > >http://www.emulation.com/pdf/skt518.pdf > >The tsop zif sockets are larger than the tsop package so you need the >extra space to solder them in place. > >-Bari -------------------------------------------------------------------- mail2web - Check your email from the web at http://mail2web.com/ .

2 1

[LinuxBIOS] Gigabyte's DualBios and recovery from a botched Linuxbios flash?
by sales＠bradbrown.com 28 Dec '05

28 Dec '05

I was preparing to flash an ECS NForce4-A939 motherboard with Linuxbios using advice I received earlier this week on this mailing list. Since the bios chip is a surface mount package, I have no easy way of restoring the original manufacturer bios image should I flash an invalid rom image to the motherboard. To minimize my risk, I planned to flash a Gigabyte motherboard with a similar chipset configuration, just to prove my image would theoreticaly work on the ECS board. This motherboard has something called Dualbios, which essentially allows you to boot from a secondary bios image should something go wrong. However, I noticed that to activate this feature and access the backup BIOS image, you had to enter the CMOS setup for the motherboard, whereas I initally assumed the backup mechanism was jumper activated. So my questions are: 1. Does anyone know if the Gigabyte Dualbios feature will still work once I flash the primary bios image with Linuxbios. If so, it would allow me to recover if my first image is bad. I don't see how it would work, since I assume Linuxbios will overwrite any recovery logic, rendering the backup bios image inaccessible. 2. Other than using a fallback image in my Linuxbios image, or using this Dualbios feature, are there any other economical ways to recover from a bad Linuxbios flash, when dealing with a non-socketed bios chip? I just have this sinking feeling that I'll flash my MB, and end up with a $75 brick, hence these questions... Thanks, Brad Brown -------------------------------------------------------------------- mail2web - Check your email from the web at http://mail2web.com/ .

4 4

Re: [LinuxBIOS] Gigabyte's DualBios and recovery from a botched Linuxbios flash?
by Young, Jeff 28 Dec '05

28 Dec '05

I can't seem to find a BIOS Savior for an 8mb chip. Does it exist? Thanks, Jeff Young -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of David Hendricks Sent: Tuesday, December 27, 2005 11:03 PM To: sales(a)bradbrown.com Cc: linuxbios(a)openbios.org Subject: Re: [LinuxBIOS] Gigabyte's DualBios and recovery from a botched Linuxbios flash? MSI does the same thing with their dual BIOS approach--I found out the hard way from purchasing a K8N-Neo3. My advice is to avoid these gimmicky 0v3rc!0ck3r BIOSes and get a BIOS Savior RD-1 or something if you can get your hands on a socketed mainboard. Or, I think someone on this list (Bari Ari?) can modify your board to use socketed flash parts as well. --David -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

1 0

Re: [LinuxBIOS] where do we stand
by Stefan Reinauer 27 Dec '05

27 Dec '05

* Young, Jeff <Jeff.Young(a)gd-ais.com> [051227 16:30]: > > Stefan, > I have tried several snapshots and none of them build correctly. > They > All have the same problem: > > /usr/lib/gcc-lib/i486-suse-linux/3.3/../../../../i486-suse-linux/bin/ld: > section .rodata.str1.32 [00000000fffbff80 -> 00000000fffc015a] overlaps > section .reset [00000000fffbfff0 -> 00000000fffbffff] > collect2: ld returned 1 exit status > make: *** [linuxbios] Error 1 > > Any ideas? The ROM_IMAGE_SIZE needs to be increased in the target Config.lb file I think. What SUSE distribution are you using? I've been compiling LinuxBIOS with gcc 3.3.x and 4.0.x for a while. 3.3 might generate larger code. Try setting ROM_IMAGE_SIZE to 0x20000. Stefan

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot