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[LinuxBIOS] Fwd: [linuxbios-checkins] r2143 - trunk/LinuxBIOSv2/src/cpu/amd/car
by yhlu 18 Dec '05

18 Dec '05

San, this is for you. You can disassembly code with HDT at CAR stage now.. YH ---------- Forwarded message ---------- From: svn(a)openbios.org <svn(a)openbios.org> Date: Dec 14, 2005 12:08 PM Subject: [linuxbios-checkins] r2143 - trunk/LinuxBIOSv2/src/cpu/amd/car To: linuxbios-checkins(a)openbios.org Author: yhlu Date: 2005-12-14 21:08:23 +0100 (Wed, 14 Dec 2005) New Revision: 2143 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: support HDT disassembly when cache as ram auto stage Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2005-12-14 02:39:33 UTC (rev 2142) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2005-12-14 20:08:23 UTC (rev 2143) @@ -1,5 +1,6 @@ /* by yhlu 6.2005 */ -/* We will use 4K bytes only */ +/* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/ +/* We may need 4K bytes only */ #define CacheSize DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) @@ -12,9 +13,9 @@ /*for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: + /* hope we can skip the double set for normal part */ #if USE_FALLBACK_IMAGE == 1 - /* check if cpu_init_detected */ movl $MTRRdefType_MSR, %ecx rdmsr @@ -22,9 +23,6 @@ movl %eax, %ebx /* We store the status */ /* Set MtrrFixDramModEn for clear fixed mtrr */ - xorl %eax, %eax - xorl %edx, %edx - enable_fixed_mtrr_dram_modify: movl $SYSCFG_MSR, %ecx rdmsr @@ -32,13 +30,6 @@ orl $SYSCFG_MSR_MtrrFixDramModEn, %eax wrmsr - /* Set the default memory type and enable fixed and variable MTRRs */ - movl $MTRRdefType_MSR, %ecx - xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000c00, %eax - wrmsr - /*Clear all MTRRs */ xorl %edx, %edx @@ -55,12 +46,6 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: - /* Enable the MTRRs and IORRs in SYSCFG */ - movl $SYSCFG_MSR, %ecx - rdmsr - orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax - wrmsr - #if CacheSize == 0x10000 /* enable caching for 64K using fixed mtrr */ movl $0x268, %ecx /* fix4k_c0000*/ @@ -69,31 +54,34 @@ wrmsr movl $0x269, %ecx wrmsr -#endif +#else -#if CacheSize == 0x8000 + #if CacheSize == 0x8000 /* enable caching for 32K using fixed mtrr */ movl $0x269, %ecx /* fix4k_c8000*/ movl $0x06060606, %eax /* WB IO type */ movl %eax, %edx wrmsr -#endif + #else /* enable caching for 16K/8K/4K using fixed mtrr */ movl $0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 + #if CacheSize == 0x4000 movl $0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 + #endif + #if CacheSize == 0x2000 movl $0x06060000, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 + #endif + #if CacheSize == 0x1000 movl $0x06000000, %edx /* WB IO type */ -#endif + #endif xorl %eax, %eax wrmsr + #endif - /* enable memory access for 0 - 1MB using top_mem */ +#endif + + /* enable memory access for first MBs using top_mem */ movl $TOP_MEM, %ecx xorl %edx, %edx movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax @@ -101,7 +89,6 @@ #endif /* USE_FALLBACK_IMAGE == 1*/ #if USE_FALLBACK_IMAGE == 0 - /* disable cache */ movl %cr0, %eax orl $(0x1<<30),%eax @@ -119,11 +106,26 @@ wrmsr movl $0x203, %ecx - movl $0x0000000f, %edx + movl $0x0000000f, %edx /* AMD 40 bit */ movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr #endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#if USE_FALLBACK_IMAGE == 1 + /* Set the default memory type and enable fixed and variable MTRRs */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + /* Enable Variable and Fixed MTRRs */ + movl $0x00000c00, %eax + wrmsr + + /* Enable the MTRRs and IORRs in SYSCFG */ + movl $SYSCFG_MSR, %ecx + rdmsr + orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax + wrmsr +#endif + /* enable cache */ movl %cr0, %eax andl $0x9fffffff,%eax @@ -132,23 +134,22 @@ #if USE_FALLBACK_IMAGE == 1 /* Read the range with lodsl*/ - movl $(CacheBase+CacheSize-4), %esi - std + cld + movl $CacheBase, %esi movl $(CacheSize>>2), %ecx rep lodsl /* Clear the range */ - movl $(CacheBase+CacheSize-4), %edi + movl $CacheBase, %edi movl $(CacheSize>>2), %ecx xorl %eax, %eax rep stosl #endif /*USE_FALLBACK_IMAGE == 1*/ - + /* set up the stack pointer */ movl $(CacheBase+CacheSize-4), %eax movl %eax, %esp - /* Restore the BIST result */ movl %ebp, %eax /* We need to set ebp ? No need */ -- To unsubscribe send an email to linuxbios-checkins+unsubscribe(a)openbios.org

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[LinuxBIOS] about make LinuxBIOS 64bit for Opteron
by Lu, Yinghai 17 Dec '05

17 Dec '05

I'm thinking to make LinuxBIOS to run at 64 bit mode so it can access 40 bit address in one instruction we just need to 1. change entry32.inc to entry64.inc... 2. change secondary.S to support 64 bit 3. change most code32 to code64 The problem is that we may need make Etherboot and mkelfImage to support 64 bit too... how do you think about it? YH

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Re: [LinuxBIOS] about make LinuxBIOS 64bit for Opteron
by Lu, Yinghai 17 Dec '05

17 Dec '05

I hate that in LinuxBIOS (CAR and RAM stage) I can not access the range above 4G, esp the last 4G in 1T Range. I could use fs base to access that, but that is quite slow... YH -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Friday, December 16, 2005 10:53 AM To: Ronald G Minnich Cc: Lu, Yinghai; Li-Ta Lo; Eric W. Biederman; LinuxBIOS Subject: Re: about make LinuxBIOS 64bit for Opteron * Ronald G Minnich <rminnich(a)lanl.gov> [051216 19:35]: > I think we have to do it. > > That said, BEFORE this effort starts, I want to make sure that EVERY > SINGLE OPTERON TARGET works as well as it did 6 months ago. And, > currently, I don't think that is the case -- see ward's letter. > > We need to get this code base back to being more solid than it currently is. I fully agree. We should make a feature freeze and only let changes in that fix something until we _verified_ that all (K8) mainboards are working and on the same level (ie. equal cmos layouts, dual core, car enabled, etc pp.) One step at a time. We just recovered. Besides that, 64bit is a must, no doubt. Stefan

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Re: [LinuxBIOS] about make LinuxBIOS 64bit for Opteron
by Brunner, Richard 16 Dec '05

16 Dec '05

If it is quite slow, then I think there is something wrong with the code. You only need to write FS base or GS base MSR once per 4GB assuming you can use 32-bit Protected non-paged mode. I don't see why this should be slower than creating page tables and populating them and doing the memory testing. I'd like to get to the bottom of this one, but on offline topic. I personally agree with Ron, we should get AMD Opteron squeaky clean first, before moving to 64-bit. > -----Original Message----- > From: linuxbios-bounces(a)openbios.org > [mailto:linuxbios-bounces@openbios.org] On Behalf Of Lu, Yinghai > Sent: Friday, December 16, 2005 11:02 AM > To: Stefan Reinauer; Ronald G Minnich > Cc: LinuxBIOS > Subject: Re: [LinuxBIOS] about make LinuxBIOS 64bit for Opteron > > I hate that in LinuxBIOS (CAR and RAM stage) I can not access > the range > above 4G, esp the last 4G in 1T Range. > > I could use fs base to access that, but that is quite slow... > > YH > > -----Original Message----- > From: Stefan Reinauer [mailto:stepan@openbios.org] > Sent: Friday, December 16, 2005 10:53 AM > To: Ronald G Minnich > Cc: Lu, Yinghai; Li-Ta Lo; Eric W. Biederman; LinuxBIOS > Subject: Re: about make LinuxBIOS 64bit for Opteron > > * Ronald G Minnich <rminnich(a)lanl.gov> [051216 19:35]: > > I think we have to do it. > > > > That said, BEFORE this effort starts, I want to make sure > that EVERY > > SINGLE OPTERON TARGET works as well as it did 6 months ago. And, > > currently, I don't think that is the case -- see ward's letter. > > > > We need to get this code base back to being more solid than it > currently is. > > I fully agree. We should make a feature freeze and only let changes in > that fix something until we _verified_ that all (K8) mainboards are > working and on the same level (ie. equal cmos layouts, dual core, car > enabled, etc pp.) > > One step at a time. We just recovered. > > Besides that, 64bit is a must, no doubt. > > Stefan > > > > > > > -- > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios > >

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[LinuxBIOS] Compiling errors for flashrom
by Christian Sühs 16 Dec '05

16 Dec '05

Hello @ all, I try to compile flashrom on my older Suse Distro 8.2 with Kernel 2.4.20 and gcc 3.3 Suse Prerelease, but it fails because of the -Werror Flag. e.g flashrom_enable.c line 408 and 417 warning: comparison between signed and unsigned ... bla, bla breaks the process. If I delete -Werror in the makefile. flashrom is build, but with many warnings shown below in mostly each file to compile. Also, flashrom doesn't work for me, I get an error "LinuxBios Table not found" and then a Segmention Fault What goes wrong? Is my gcc version to old? pciutils are installed. regards Chris

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Re: [LinuxBIOS] Compiling errors for flashrom
by Richard Smith 15 Dec '05

15 Dec '05

On 12/15/05, Christian Sühs <chris(a)suehsi.de> wrote: > BTW: GCC 2.96 compiles the flashrom tool without any warnings and > errors. At time it seems the tool works correct. It recognized the right > chipset and the right EEProm Chip. What flash part (EEProm) is on that board ? > But unfortunatly gcc 2.96 fails to compile the LinuxBios Image :D > However, if I recieve my chip I will try to flash LB with the 2.96 > compiled flashtool and the gcc 3.3 compiled image ;) and see what happens. What SVN rev are you using? I thought Stefan reciently fixed up all the compile and alignment issues to work with newer compilers. Its ok if flashrom and the linuxbios image are compiled with different compilers. -- Richard A. Smith

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Re: [LinuxBIOS] Compiling errors for flashrom
by Richard Smith 14 Dec '05

14 Dec '05

> > > > Do you have a linuxbios table in your image? > > Oh, is their any what I understand wrong? > I thougt flashrom is a binary to flash rom images into EEProms. > It is but it looks for a linuxbios table to see what mfg and mainboard that image was built for. > I have called it without any parameters and it should spoke out > something about my board and my bios, like the output in the documentation. Hmm.. Dunno. You will have to look at the source to figure out why that fails. > However, I will try to get work LinuxBios on my VIA Epia ML. > Therefor I have done any step in the Epia HOWTO. I think their is a > linuxbios table in my image. But before I try the image, I will wait for > my second EEProm :D I think those howto's are pretty old. They should probally be more of a guide rather than a reciepe. -- Richard A. Smith

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Re: [LinuxBIOS] tyan s2881
by Lu, Yinghai 13 Dec '05

13 Dec '05

Ron, Are you using flash_rom or flashrom? Stepan put sth in flashrom to check the LinuxBIOS image size=262144 MANUFACTURER: Tyan MAINBOARD ID: s2881 YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Ward Vandewege Sent: Monday, December 12, 2005 6:05 PM To: Ronald G Minnich Cc: LinuxBIOS Subject: Re: [LinuxBIOS] tyan s2881 On Mon, Dec 12, 2005 at 05:25:48PM -0700, Ronald G Minnich wrote: > we use the v2 flashrom all the time on s2881 here. > > Also, Ward led me to believe he was getting serial output. Did I miss > something? Ah, sorry about the confusion, I get serial output when NOT running linuxbios. That was just me making sure that was set up correctly. I haven't yet managed to boot linuxbios. I'm obviously doing something stupid building the image - my images are not even being recognized by flashrom as being Linuxbios images. Yhlu sent me an image to test, but I can't burn that as it is being seen as not the correct size by flashrom. Real size: 524288 bytes flashrom: root@chimera:~/LinuxBIOSv2/util/flashrom# ./flashrom -v -w ../../../s2881_linuxbios.rom Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on AMD8111...OK Pm49FL004 found at physical address: 0xfff80000 Flash part is Pm49FL004 LinuxBIOS image size=262144 MANUFACTURER: Tyan MAINBOARD ID: s2881 ERROR: This firmware image does not fit to this machine Override with -m ifyou know exactly what you are doing. Not sure what's going on here. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

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[LinuxBIOS] EPoX 8KTA3 Mainboard
by Keven L. Ates 13 Dec '05

13 Dec '05

Hello All, Can anyone give me some feedback on using LinuxBIOS on the following: EPoX 8KTA3 Mainboard AMD Athlon 1GHz Socket A "lspci" output follows AGP Video Card - ATI Radeon PLCC with Award BIOS v6.0 (flashed updates with awdflash.exe) Some MBs may also have an optional RAID chip. http://www.epox.com/USA/product.asp?ID=EP-8KTA3 As it uses VIA chip I'm hoping for the best. I'm currently using SuSE Linux 9.3 (2.6 Kernel) and Windows 2000 booting from GRUB on the MBR of boot partition and would like LinuxBIOS to call the MBR (so LinuxBIOS only needs to do the minimum). NOTE: It seems to me that much of the configuration of a system can be derived from a linux installation directly such that the LinuxBIOS make can "read" a system its compiling on and set itself up. Particularly, it could "lspci", read the active BIOS or a supplied BIOS file for the video, etc. with very little user intervention and create an appropriate LinuxBIOS for the machine. Yeah, I know, what if you need to compile on one machine and feed to another? But, how about a "what if you don't" option? Could it be made to do it automagically? linux:~ # lspci -vvv 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133] (rev 03) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ Latency: 8 Region 0: Memory at d8000000 (32-bit, prefetchable) Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x4 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT8363/8365 [KT133/KM133 AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: dc000000-ddffffff Prefetchable memory behind bridge: d0000000-d7ffffff Expansion ROM at 0000a000 [disabled] [size=4K] BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at b000 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.2 USB Controller: VIA Technologies, Inc. USB (rev 16) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32, cache line size 08 Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at b400 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.3 USB Controller: VIA Technologies, Inc. USB (rev 16) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32, cache line size 08 Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at b800 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin ? routed to IRQ 9 Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686 AC97 Audio Controller (rev 50) Subsystem: VIA Technologies, Inc. Onboard Audio on EP7KXA Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at bc00 Region 1: I/O ports at c000 [size=4] Region 2: I/O ports at c400 [size=4] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 08) Subsystem: Creative Labs CT4760 SBLive! Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (500ns min, 5000ns max) Interrupt: pin A routed to IRQ 3 Region 0: I/O ports at c800 Capabilities: [dc] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:08.1 Input device controller: Creative Labs SB Live! MIDI/Game Port (rev 08) Subsystem: Creative Labs Gameport Joystick Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 0: I/O ports at cc00 Capabilities: [dc] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:09.0 Unknown mass storage controller: Promise Technology, Inc. 20262 (rev 01) Subsystem: Promise Technology, Inc. Ultra66 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at d000 Region 1: I/O ports at d400 [size=4] Region 2: I/O ports at d800 [size=8] Region 3: I/O ports at dc00 [size=4] Region 4: I/O ports at e000 [size=64] Region 5: Memory at df000000 (32-bit, non-prefetchable) [size=128K] 0000:00:0a.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller Subsystem: Netgear FA311 / FA312 (FA311 with WoL HW) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2750ns min, 13000ns max) Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at e400 Region 1: Memory at df020000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ 0000:00:0b.0 Ethernet controller: National Semiconductor Corporation DP83815 (MacPhyter) Ethernet Controller Subsystem: Netgear FA311 / FA312 (FA311 with WoL HW) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2750ns min, 13000ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at e800 Region 1: Memory at df021000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=320mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:01:00.0 VGA compatible controller: ATI Technologies Inc Radeon R100 QD [Radeon 7200] (prog-if 00 [VGA]) Subsystem: ATI Technologies Inc Radeon AIW Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (2000ns min), cache line size 08 Interrupt: pin A routed to IRQ 3 Region 0: Memory at d0000000 (32-bit, prefetchable) Region 1: I/O ports at a000 [size=256] Region 2: Memory at dd000000 (32-bit, non-prefetchable) [size=512K] Capabilities: [58] AGP version 2.0 Status: RQ=48 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=32 ArqSz=0 Cal=0 SBA+ AGP+ GART64- 64bit- FW- Rate=x4 Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME-

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[LinuxBIOS] tyan s2881
by Ward Vandewege 13 Dec '05

13 Dec '05

Hi there, First of all, thanks for upgrading the SVN tree, it now compiles without problems (but still lots of warnings ;) for the Tyan s2881. I've managed to build a Linuxbios image, using FILO 0.5 and the latest subversion revision of the Linuxbios tree (2141). So I've compiled filo, built the rom image, and burned the rom into our biossavior. This is the filo configuration file I used: USE_GRUB = 1 MENULST_FILE = "sda1:/grub/menu.lst" AUTOBOOT_FILE = "sda1:/vmlinuz-2.6.12-9-amd64-generic root=/dev/sda4 console=tty0 console=ttyS0,19200n8" AUTOBOOT_DELAY = 4 IDE_DISK = 1 VGA_CONSOLE = 1 PC_KEYBOARD = 1 SERIAL_CONSOLE = 1 SERIAL_IOBASE = 0x3f8 SERIAL_SPEED = 19200 FSYS_EXT2FS = 1 FSYS_FAT = 1 FSYS_REISERFS = 1 FSYS_ISO9660 = 1 ELTORITO = 1 SUPPORT_PCI = 1 PCI_BRUTE_SCAN = 1 LINUX_LOADER = 1 PCI_CONFIG_1 = 1 I'm unsure about the references to sda in the MENULST_FILE and AUTOBOOT_FILE parameters. This is how my running kernel sees the SATA drives; Linuxbios supports booting from SATA, right? The Config.lb I'm using is: target s2881 mainboard tyan/s2881 # Tyan s2881 romimage "normal" option ROM_SIZE = 475136 option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" payload ../../../../../payloads/filo.elf end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ../../../../../payloads/filo.elf end That's pretty much the stock version from the SVN tree. I used the flashrom tool to burn & verify the image. That works perfectly. Unfortunately, when trying to boot it, nothing happens. Nothing on the screen (but I didn't expect that as I'm still not clear about the whole vga bios thing). I've hooked up another linux box for capturing the serial output, and verified that that setup works (serial login to s2881 works, running the proprietary bios). When booting linuxbios, there is no output on the serial line. This MB has POST leds onboard; when booting from poweroff, they remain stuck at FF when using the linuxbios image. When booting the proprietary image, they cycle through a whole range of numbers, to finish on 00 once the system is up. I have a feeling I'm missing something important. Any pointers? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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