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Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

I fixed one merge typo in src/southbride/amd/amd8111/amd8111_early_ctrl.c Please change 15 to 11 at line 13. YH -----Original Message----- From: Ward Vandewege [mailto:ward@gnu.org] Sent: Friday, April 07, 2006 1:07 PM To: Lu, Yinghai Cc: Ronald G Minnich; linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK On Fri, Apr 07, 2006 at 12:49:10PM -0700, Lu, Yinghai wrote: > Can you send your cache_as_ram_auto.c and Config.lb in > src/mainboard/tyan/s2881? Sure, they are attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

Ward, Can you send your cache_as_ram_auto.c and Config.lb in src/mainboard/tyan/s2881? YH -----Original Message----- From: Ronald G Minnich [mailto:rminnich@lanl.gov] Sent: Friday, April 07, 2006 12:39 PM To: Lu, Yinghai Cc: Ward Vandewege; linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK Lu, Yinghai wrote: > The Image that you built has problem with HT reset. > It may still work at 200Mhz 8 bit HT speed. And some errata fix is not > effective too. So, YH, what can he do about it? thanks ron

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Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

The Image that you built has problem with HT reset. It may still work at 200Mhz 8 bit HT speed. And some errata fix is not effective too. YH -----Original Message----- From: Ward Vandewege [mailto:ward@gnu.org] Sent: Friday, April 07, 2006 11:46 AM To: Lu, Yinghai Cc: Ronald G Minnich; linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK On Fri, Apr 07, 2006 at 11:32:30AM -0700, Lu, Yinghai wrote: > Wait, you image has problem. > > After print ht reset - > The soft_reset() doesn't cause reset... I'm not sure I understand; could you elaborate a bit? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

Wait, you image has problem. After print ht reset - The soft_reset() doesn't cause reset... YH

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Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK
by Lu, Yinghai 07 Apr '06

07 Apr '06

Committed. Also enable HT 1GHz support for s2891 and s2892. Thanks Yinghai Lu -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Lu, Yinghai Sent: Friday, March 31, 2006 5:24 PM To: Ronald G Minnich; Stefan Reinauer; Jason Schildt Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] CONFIG_LB_MEM_TOPK Svn diff to current tree. Please check it. I will commit it some time next week. Guys have problem with s2891, s2881, s2892, please try it by patch -p0 to the latest tree. Changes 1. new CAR with copy data from cache to ram 2. new coherent_ht_car.c 3. new reset code for amd8111 4. new amd8111_early_ctrl without sysinfo... Thanks Yinghai Lu

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[LinuxBIOS] xp booting
by Stefan Reinauer 07 Apr '06

07 Apr '06

Hi, there's been quite some effort to get Windows XP running on Apple's new Intel Macs. And not all of it was by Apple. Interesting is that one guy opened his source code of an EFI compatibility handler. Maybe it is a good inspiration for LinuxBIOS? http://daemons.net/~clay/index.php/2006/03/15/dual-booting-windows-xp-and-m… http://daemons.net/~clay/OSXP/ Stefan

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Re: [LinuxBIOS] bus 0 dev 0 and fidvid change
by Lu, Yinghai 04 Apr '06

04 Apr '06

so what exactly does this do? It sets the position of an 8131 on a given bus? Does this work for all 8131 in a system? What about the 8111? And that 0 value - is that a special case? What is the connection to the other functionality? Does that mean there is only an 8111 and no 8131? Possible values: 0, 1, 6 ? Others? > HT_CHAIN_END_UNITID_BASE > Default is 0x20 --- mean do not use that, if it is 0, the > amd8111 will be dev0 do not use what? so i read: - HT_CHAIN_END_UNITID_BASE == 0x20: 8111 on bus 1 - HT_CHAIN_END_UNITID_BASE == 0x00: 8111 on bus 0 why end unitid base? how is the correlation to HT_CHAIN_UNITID_BASE? Possible values: 0, 32 ? Others? YH: A) 8131/8111 HT_CHAIN_UNITID_BASE=0x10, HT_CHAIN_END_UNITID_BASE=0x06 So 8131 will start from 0x10, and 8111 will start from 0x06 B) ck804 only HT_CHAIN_UNITD_BASE=0, So ck804 will start from 0x00. > SB_HT_CHAIN_UNITID_OFFSET_ONLY > Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset > unitid of SB CHAIN. Possible values: 0, 1? Others? What does that mean? Why would I only want to offset the unitid of the SB? SB Chain? Does it change the meaning of HT_CHAIN_UNITID_BASE? YH: 0: mean using HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE. > K8_SB_HT_CHAIN_ON_BUS0 > Deault is 0, if it is 1, will put sb chain on bus 0, even for > S2885 sb ht is on link2, it will put on bus0. does this require an 8111 southbrigde? YH: any SB chain > K8_SET_FIDVID in cache_as_ram_auto.c or auto.c > Fidvid change to sync the fid on 4 way or more system with different cpu > installed.... I thought SMP systems need identical CPUs installed, according to AMD BKDG? Is this option dangerous? Does it downclock faster CPUs to work sanely in SMP context? YH: A) using different CPU B) some MB can not use at MAX fid.... > Put following sequence in your cache_as_ram_auto.c after ht is set. > enable_fid_change(); > enable_fid_change_on_sb(); > init_fidvid_bsp(bsp_apicid); This is only needed if I want to use different CPUs? > please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for > detail.... Stefan

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[LinuxBIOS] bus 0 dev 0 and fidvid change
by Lu, Yinghai 04 Apr '06

04 Apr '06

Please check the issue 41, I make K8 MB can be compiled, and It include bus0/dev0 and fidvid change enhancement HT_CHAIN_UNITID_BASE Default is 1, and if it is 6, then amd8131 will be from 6, also if it is 0, will assume ht chain only have one HT device... HT_CHAIN_END_UNITID_BASE Default is 0x20 --- mean do not use that, if it is 0, the amd8111 will be dev0 SB_HT_CHAIN_UNITID_OFFSET_ONLY Default is 1, so if HT_CHAIN_UNITID_BASE!=1, will only offset unitid of SB CHAIN. K8_SB_HT_CHAIN_ON_BUS0 Deault is 0, if it is 1, will put sb chain on bus 0, even for S2885 sb ht is on link2, it will put on bus0. K8_SET_FIDVID in cache_as_ram_auto.c or auto.c Fidvid change to sync the fid on 4 way or more system with different cpu installed.... Put following sequence in your cache_as_ram_auto.c after ht is set. enable_fid_change(); enable_fid_change_on_sb(); init_fidvid_bsp(bsp_apicid); please check init_cpus.c and fidvid.c and amd8111_early_ctrl.c for detail.... YH

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[LinuxBIOS] Geode Utilities and Tools
by Bari Ari 04 Apr '06

04 Apr '06

Just FYI on the Geodes in case anyone missed them... The AMD Geode dev site has a few handy utilities and tools for debugging BIOS and driver settings. Cyreg - Cyreg is a menu driven utility that displays memory, I/O and PCI configuration space data. The menus are defined in a text file that allows the user to easily modify each menu. Loadreg - Loadreg is a command line utility that allows the user to read or modify any I/O, memory, or PCI configuration space location. It is ideally suited to modifying system registers via a batch file. MCVAL - Mcval tests the state of the memory controller against known values, as well as lists all supported processor speeds and their associated memory controller register values. -Bari

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Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards.
by Lu, Yinghai 04 Apr '06

04 Apr '06

Yes. -----Original Message----- From: Stefan Reinauer [mailto:stepan@coresystems.de] Sent: Monday, April 03, 2006 3:55 PM To: Lu, Yinghai Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] [linuxbios-checkins] r2232 breaks all opteron boards. * Lu, Yinghai <yinghai.lu(a)amd.com> [060403 23:25]: > Fixed. Please check again. It builds fine again. thanks. Should we drop reset.c from all amd64 mainboards? Stefan -- coresystems GmbH * Brahmsstr. 16 * D-79104 Freiburg i. Br. Tel.: +49 761 7668825 * Fax: +49 761 7664613 Email: info(a)coresystems.de * http://www.coresystems.de/

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